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586/686 Processors Chart

486 | 586 / 686 | 786 | Current

This list is not comprehensive.


Pentium (P5)
Intel
Processors		Natural
State		SocketsL1 Cache
(Associativity)		Transistors
Pentium 60
(P5)
March 22, 1993 - {$878}		273 pins
60MHz (60x1.0)
5v		Socket 48KB data (2-way)
8KB instruction (2-way)		3.1 million
0.8µm process
296mm² die
Pentium 66
(P5)
March 22, 1993 - {$965}		273 pins
66MHz (66x1.0)
5v		Socket 48KB data (2-way)
8KB instruction (2-way)		3.1 million
0.8µm process
296mm² die
PentiumODP5V 120
(P5T)
March 4, 1996 - {$399}		273 pins
120MHz (60x2.0)
5v		Socket 48KB data (2-way)
8KB instruction (2-way)		3.3 million
0.35µm process
90mm² die
PentiumODP5V 133
(P5T)
March 4, 1996 - {$399}		273 pins
133MHz (66x2.0)
5v		Socket 48KB data (2-way)
8KB instruction (2-way)		3.3 million
0.35µm process
90mm² die


Pentium Classic (P54C)
AMD
Processors		Natural
State		SocketsL1 Cache
(Associativity)		Transistors
K5 PR75
(SSA5 - Model 0)
March 27, 1996 - {$75}		296 pins
75MHz (50x1.5)
3.52v		Socket 78KB data (4-way)
16KB instruction (4-way)		4.3 million
0.5µm process
271mm² die
0.35µm process
161mm² die
K5 PR90
(SSA5 - Model 0)
March 27, 1996 - {$99}		296 pins
90MHz (60x1.5)
3.52v		Socket 78KB data (4-way)
16KB instruction (4-way)		4.3 million
0.35µm process
161mm² die
K5 PR100
(SSA5 - Model 0)
June 17, 1996 - {$84}		296 pins
100MHz (66x1.5)
3.52v		Socket 78KB data (4-way)
16KB instruction (4-way)		4.3 million
0.35µm process
161mm² die
K5 PR120
(5k86 - Model 1)
October 7, 1996 - {$106}		296 pins
90MHz (60x1.5)
3.52v		Socket 78KB data (4-way)
16KB instruction (4-way)		4.3 million
0.35µm process
181mm² die
K5 PR133
(5k86 - Model 1)
October 7, 1996 - {$134}		296 pins
100MHz (66x1.5)
3.52v		Socket 78KB data (4-way)
16KB instruction (4-way)		4.3 million
0.35µm process
181mm² die
K5 PR150
(5k86 - Model 2)
January 13, 1997		296 pins
105MHz (60x1.75)
3.52v		Socket 78KB data (4-way)
16KB instruction (4-way)		4.3 million
0.35µm process
181mm² die
K5 PR166
(5k86 - Model 2/3)
January 13, 1997		296 pins
116MHz (66x1.75)
3.52v		Socket 78KB data (4-way)
16KB instruction (4-way)		4.3 million
0.35µm process
181mm² die
K5 PR200
(5k86 - Model 3)
1Q 1997		296 pins
133MHz (66x2.0)
3.52v		Socket 78KB data (4-way)
16KB instruction (4-way)		4.3 million
0.35µm process
181mm² die
Cyrix
Processors		Natural
State		SocketsL1 Cache
(Associativity)		Transistors
6x86 PR90+
(M1)
Manuf: SGS
November 1995		296 pins
80MHz (40x2.0)
3.3v		Socket 716KB unified (4-way)3.0 million
0.65µm 3M process
394mm² die
6x86 PR120+
(M1)
Manuf: SGS
October 9, 1995 - {$450}		296 pins
100MHz (50x2.0)
3.3v		Socket 716KB unified (4-way)3.0 million
0.65µm 3M process
394mm² die
6x86 PR133+
(M1R)
Manuf: IBM
February 5, 1996 - {$326}		296 pins
110MHz (55x2.0)
3.3v		Socket 716KB unified (4-way)3.0 million
0.65µm 5M process
225mm² die
6x86 PR150+
(M1R)
Manuf: IBM
February 5, 1996 - {$451}		296 pins
120MHz (60x2.0)
3.3v or 3.52v		Socket 716KB unified (4-way)3.0 million
0.65µm 5M process
225mm² die
6x86 PR166+
(M1R)
Manuf: IBM
February 5, 1996 - {$621}		296 pins
133MHz (66x2.0)
3.3v or 3.52v		Socket 716KB unified (4-way)3.0 million
0.65µm 5M process
225mm² die
6x86 PR200+
(M1R)
Manuf: IBM
June 3, 1996 - {$499}		296 pins
150MHz (75x2.0)
3.52v		Socket 716KB unified (4-way)3.0 million
0.44µm 5M process
?mm² die
6x86L PR120+
(M1L)
January 1997		296 pins
100MHz (50x2.0)
2.8v/3.3v split		Socket 716KB unified (4-way)3.0 million
0.35µm 5M process
169mm² die
6x86L PR133+
(M1L)
February 1997		296 pins
110MHz (55x2.0)
2.8v/3.3v split		Socket 716KB unified (4-way)3.0 million
0.35µm 5M process
169mm² die
6x86L PR150+
(M1L)
March 1997		296 pins
120MHz (60x2.0)
2.8v/3.3v split		Socket 716KB unified (4-way)3.0 million
0.35µm 5M process
169mm² die
6x86L PR166+
(M1L)
April 1997		296 pins
133MHz (66x2.0)
2.8v/3.3v split		Socket 716KB unified (4-way)3.0 million
0.35µm 5M process
169mm² die
6x86L PR200+
(M1L)
April 1997		296 pins
150MHz (75x2.0)
2.8v/3.3v split		Socket 716KB unified (4-way)3.0 million
0.35µm 5M process
169mm² die
Cx5gx86 120
(MediaGX)
February 20, 1997 - {$79}		352 pin BGA
120MHz (60x2.0)
3.3v		Proprietary16KB unified2.4 million
0.6µm process
160mm² die
Cx5gx86 133
(MediaGX)
February 20, 1997 - {$99}		352 pin BGA
133MHz (66x2.0)
3.3v		Proprietary16KB unified2.4 million
0.6µm process
160mm² die
Cx5gx86 150
(MediaGXi)
June 6, 1997 - {$99}		352 pin BGA
150MHz (60x2.5)
2.5v		Proprietary16KB unified2.4 million
0.5µm process
160mm² die
Cx5gx86 166
(MediaGXi)
June 30, 1997 - {$88}		352 pin BGA
166MHz (66x2.5)
2.5v		Proprietary16KB unified2.4 million
0.5µm process
160mm² die
Cx5gx86 180
(MediaGXi)
June 30, 1997 - {$121}		352 pin BGA
180MHz (60x3.0)
2.5v		Proprietary16KB unified2.4 million
0.5µm process
160mm² die
Intel
Processors		Natural
State		SocketsL1 Cache
(Associativity)		Transistors
Pentium 75
(P54C)
October 10, 1994 - {$535}		296 pins
75MHz (50x1.5)
MD,STD,VRT		Socket 5
Socket 7		8KB data (2-way)
8KB instruction (2-way)		3.2 million
0.6µm process
148mm² die
Pentium 90
(P54C)
March 7, 1994 - {$849}		296 pins
90MHz (60x1.5)
MD,STD,VR,VRT		Socket 5
Socket 7		8KB data (2-way)
8KB instruction (2-way)		3.2 million
0.6µm process
148mm² die
Pentium 100
(P54C)
March 7, 1994 - {$995}		296 pins
100MHz (66x1.5)
100MHz (50x2.0)
MD,STD,VR,VRE,VRT		Socket 5
Socket 7		8KB data (2-way)
8KB instruction (2-way)		3.2 million
0.6µm process
148mm² die
Pentium 120
(P54CQS)
March 27, 1995 - {$935}		296 pins
120MHz (60x2.0)
MD,STD,VRE,VRT		Socket 5
Socket 7		8KB data (2-way)
8KB instruction (2-way)		3.3 million
0.35µm process
90mm² die
Pentium 133
(P54CS)
June 12, 1995 - {$935}		296 pins
133MHz (66x2.0)
MD,STD,VRE,VRT		Socket 5
Socket 7		8KB data (2-way)
8KB instruction (2-way)		3.3 million
0.35µm process
90mm² die
Pentium 150
(P54CS)
January 4, 1996 - {$547}		296 pins
150MHz (60x2.5)
STD,VRT		Socket 78KB data (2-way)
8KB instruction (2-way)		3.3 million
0.35µm process
90mm² die
Pentium 166
(P54CS)
January 4, 1996 - {$749}		296 pins
166MHz (66x2.5)
VRE		Socket 78KB data (2-way)
8KB instruction (2-way)		3.3 million
0.35µm process
90mm² die
Pentium 200
(P54CS)
June 10, 1996 - {$599}		296 pins
200MHz (66x3.0)
VRE		Socket 78KB data (2-way)
8KB instruction (2-way)		3.3 million
0.35µm process
90mm² die
PentiumODP3V 125
(P54CT)
March 4, 1996 - {$399}		320 pins
125MHz (50x2.5)
3.135v~3.600v		Socket 5
Socket 7		8KB data (2-way)
8KB instruction (2-way)		3.3 million
0.35µm process
90mm² die
PentiumODP3V 150
(P54CT)
May 1996		320 pins
150MHz (60x2.5)
3.135v~3.600v		Socket 5
Socket 7		8KB data (2-way)
8KB instruction (2-way)		3.3 million
0.35µm process
90mm² die
PentiumODP3V 166
(P54CT)
May 1996		320 pins
166MHz (66x2.5)
3.135v~3.600v		Socket 5
Socket 7		8KB data (2-way)
8KB instruction (2-way)		3.3 million
0.35µm process
90mm² die


Pentium MMX (P55C)
AMD
Processors		Natural
State		SocketsL1 Cache
(Associativity)		Transistors
K6 166 MMX
(Model 6)
April 2, 1997 - {$244}		321 pins
166MHz (66x2.5)
2.9v/3.3v split		Socket 732KB data (2-way)
32KB instruction (2-way)		8.8 million
0.35µm process
162mm² die
K6 200 MMX
(Model 6)
April 2, 1997 - {$349}		321 pins
200MHz (66x3.0)
2.9v/3.3v split		Socket 732KB data (2-way)
32KB instruction (2-way)		8.8 million
0.35µm process
162mm² die
K6 233 MMX
(Model 6)
April 2, 1997 - {$469}		321 pins
233MHz (66x3.5)
3.2v/3.3v split
3.3v/3.3v split		Socket 732KB data (2-way)
32KB instruction (2-way)		8.8 million
0.35µm process
162mm² die
K6 233 MMX
(Little Foot - Model 7) - mobile chip
January 6, 1998		321 pins
233MHz (66x3.5)
2.2v/3.3v split		Socket 732KB data (2-way)
32KB instruction (2-way)		8.8 million
0.25µm process
68mm² die
K6 266 MMX
(Little Foot - Model 7)
January 6, 1998 - {$268}		321 pins
266MHz (66x4.0)
2.2v/3.3v split		Socket 732KB data (2-way)
32KB instruction (2-way)		8.8 million
0.25µm process
68mm² die
K6 300 MMX
(Little Foot - Model 7)
April 7, 1998 - {$246}		321 pins
300MHz (66x4.5)
2.2v/3.45v split		Socket 732KB data (2-way)
32KB instruction (2-way)		8.8 million
0.25µm process
68mm² die
K6-2 266 MMX 3DNow!
(Chompers - Model 8)
May 28, 1998 - {$185}		321 pins
266MHz (66x4.0)
2.2v/3.3v split		Socket 732KB data (2-way)
32KB instruction (2-way)		9.3 million
0.25µm process
81mm² die
K6-2 300 MMX 3DNow!
(Chompers - Model 8)
May 28, 1998 - {$281}		321 pins
300MHz (100x3.0)
2.2v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)		9.3 million
0.25µm process
81mm² die
K6-2 333 MMX 3DNow!
(Chompers - Model 8)
May 28, 1998 - {$369}		321 pins
333MHz (95x3.5)
2.2v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)		9.3 million
0.25µm process
81mm² die
K6-2 350 MMX 3DNow!
(Chompers - Model 8)
August 27, 1998 - {$317}		321 pins
350MHz (100x3.5)
2.2v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)		9.3 million
0.25µm process
81mm² die
K6-2 300 MMX 3DNow!
(Chompers - Model 8 CXT)
November 16, 1998		321 pins
300MHz (100x3.0)
300MHz (66x4.5)
2.2v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)		9.3 million
0.25µm process
81mm² die
K6-2 333 MMX 3DNow!
(Chompers - Model 8 CXT)
November 16, 1998		321 pins
333MHz (95x3.5)
333MHz (66x5.0)
2.2v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)		9.3 million
0.25µm process
81mm² die
K6-2 350 MMX 3DNow!
(Chompers - Model 8 CXT)
November 16, 1998		321 pins
350MHz (100x3.5)
2.2v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)		9.3 million
0.25µm process
81mm² die
K6-2 366 MMX 3DNow!
(Chompers - Model 8 CXT)
November 16, 1998 - {$187}		321 pins
366MHz (66x5.5)
2.2v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)		9.3 million
0.25µm process
81mm² die
K6-2 380 MMX 3DNow!
(Chompers - Model 8 CXT)
November 16, 1998 - {$213}		321 pins
380MHz (95x4.0)
2.2v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)		9.3 million
0.25µm process
81mm² die
K6-2 400 MMX 3DNow!
(Chompers - Model 8 CXT)
November 16, 1998 - {$283}		321 pins
400MHz (100x4.0)
2.2v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)		9.3 million
0.25µm process
81mm² die
K6-2 450 MMX 3DNow!
(Chompers - Model 8 CXT)
February 26, 1999 - {$203}		321 pins
450MHz (100x4.5)
2.2v/3.3v split (Aug 99)
2.4v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)		9.3 million
0.25µm process
81mm² die
K6-2 475 MMX 3DNow!
(Chompers - Model 8 CXT)
April 5, 1999 - {$213}		321 pins
475MHz (95x5.5)
2.2v/3.3v split (Aug 99)
2.4v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)		9.3 million
0.25µm process
81mm² die
K6-2 500 MMX 3DNow!
(Chompers - Model 8 CXT)
August 30, 1999 - {$167}		321 pins
500MHz (100x5.0)
2.2v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)		9.3 million
0.25µm process
81mm² die
K6-2 533 MMX 3DNow!
(Chompers - Model 8 CXT)
November 29, 1999 - {$167}		321 pins
533MHz (97x5.5)
2.2v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)		9.3 million
0.25µm process
81mm² die
K6-2 550 MMX 3DNow!
(Chompers - Model 8 CXT)
February 22, 2000 - {$189}		321 pins
550MHz (100x5.5)
2.3v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)		9.3 million
0.25µm process
81mm² die
K6-III 400 MMX 3DNow!
(Sharptooth - Model 9)
February 22, 1999 - {$284}		321 pins
400MHz (100x4.0)
2.2v/3.3v split (Sep 99)
2.4v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		21.3 million
0.25µm process
118mm² die
K6-III 450 MMX 3DNow!
(Sharptooth - Model 9)
February 22, 1999 - {$476}		321 pins
450MHz (100x4.5)
2.2v/3.3v split (Sep 99)
2.4v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		21.3 million
0.25µm process
118mm² die
K6-2+ 450 MMX 3DNow!
(?) - mobile chip
April 18, 2000 - {$85}		321 pins
450MHz (100x4.5)
2.0v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		? million
0.18µm process
?mm² die
K6-2+ 475 MMX 3DNow!
(?) - mobile chip
April 18, 2000 - {$98}		321 pins
475MHz (95x5.0)
2.0v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		? million
0.18µm process
?mm² die
K6-2+ 500 MMX 3DNow!
(?) - mobile chip
April 18, 2000 - {$112}		321 pins
500MHz (100x5.0)
2.0v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		? million
0.18µm process
?mm² die
K6-2+ 533 MMX 3DNow!
(?) - mobile chip
June 26, 2000 - {$85}		321 pins
533MHz (97x5.5)
2.0v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		? million
0.18µm process
?mm² die
K6-2+ 550 MMX 3DNow!
(?) - mobile chip
June 26, 2000 - {$99}		321 pins
550MHz (100x5.5)
2.0v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		? million
0.18µm process
?mm² die
K6-III+ 450 MMX 3DNow!
(?) - mobile chip
April 18, 2000 - {$140}		321 pins
450MHz (100x4.5)
2.0v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		? million
0.18µm process
?mm² die
K6-III+ 475 MMX 3DNow!
(?) - mobile chip
April 18, 2000 - {$162}		321 pins
475MHz (95x5.0)
2.0v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		? million
0.18µm process
?mm² die
K6-III+ 500 MMX 3DNow!
(?) - mobile chip
April 18, 2000 - {$184}		321 pins
500MHz (100x5.0)
2.0v/3.3v split		Super 732KB data (2-way)
32KB instruction (2-way)
256KB on-Die unified L2 (4-way)
* 4GB cacheable		? million
0.18µm process
?mm² die
Centaur
Processors		Natural
State		SocketsL1 Cache
(Associativity)		Transistors
IDT Winchip 150 MMX
(C6)
[not released]		296 pins
150MHz (75x2.0)
3.3v		Socket 732KB data (2-way)
32KB instruction (2-way)		5.4 million
0.35µm process
88mm² die
IDT Winchip 180 MMX
(C6)
October 13, 1997 - {$90}		296 pins
180MHz (60x3.0)
3.3v or 3.52v		Socket 732KB data (2-way)
32KB instruction (2-way)		5.4 million
0.35µm process
88mm² die
IDT Winchip 200 MMX
(C6)
October 13, 1997 - {$135}		296 pins
200MHz (66x3.0)
3.3v or 3.52v		Socket 732KB data (2-way)
32KB instruction (2-way)		5.4 million
0.35µm process
88mm² die
IDT Winchip 225 MMX
(C6)
December 1997		296 pins
225MHz (75x3.0)
3.52v		Socket 732KB data (2-way)
32KB instruction (2-way)		5.4 million
0.35µm process
88mm² die
IDT Winchip 240 MMX
(C6)
December 1997		296 pins
240MHz (60x4.0)
3.52v		Socket 732KB data (2-way)
32KB instruction (2-way)		5.4 million
0.35µm process
88mm² die
IDT Winchip-2 200 MMX 3DNow!
(C6+)		296 pins
200MHz (66x3.0)
3.3v or 3.52v		Socket 732KB data (4-way)
32KB instruction (2-way)		6.0 million
0.25µm process
58mm² die
IDT Winchip-2 225 MMX 3DNow!
(C6+)
October 13, 1998		296 pins
225MHz (75x3.0)
3.3v or 3.52v		Socket 732KB data (4-way)
32KB instruction (2-way)		6.0 million
0.25µm process
58mm² die
IDT Winchip-2 240 MMX 3DNow!
(C6+)
October 13, 1998		296 pins
240MHz (60x4.0)
3.3v or 3.52v		Socket 732KB data (4-way)
32KB instruction (2-way)		6.0 million
0.25µm process
58mm² die
IDT Winchip-2A 200 MMX 3DNow!
(C6+)
May 1999		296 pins
200MHz (66x3.0)
3.3v or 3.52v		Socket 732KB data (4-way)
32KB instruction (2-way)		6.0 million
0.25µm process
58mm² die
IDT Winchip-2A 233 MMX 3DNow!
(C6+)
May 1999		296 pins
233MHz (66x3.5)
3.3v or 3.52v		Socket 732KB data (4-way)
32KB instruction (2-way)		6.0 million
0.25µm process
58mm² die
IDT Winchip-2A 266 MMX 3DNow!
(C6+)
May 1999		296 pins
233MHz (100x2.33)
3.52v		Socket 732KB data (4-way)
32KB instruction (2-way)		6.0 million
0.25µm process
58mm² die
IDT Winchip-2B 200 MMX 3DNow!
(C6+)
[engineering sample only]		296 pins
200MHz (66x3.0)
2.8v/3.3v split		Super 732KB data (4-way)
32KB instruction (2-way)		6.0 million
0.18µm process
69mm² die
IDT Winchip-2B 233 MMX 3DNow!
(C6+)
[not released]		296 pins
200MHz (100x2.0)
2.8v/3.3v split		Super 732KB data (4-way)
32KB instruction (2-way)		6.0 million
0.18µm process
69mm² die
IDT Winchip-3 233 MMX 3DNow!
(C6-2L)
[engineering sample only]		296 pins
200MHz (66x3.0)
2.8v/3.3v split		Socket 764KB data (4-way)
64KB instruction (2-way)		10.2 million
0.25µm process
76mm² die
IDT Winchip-3 266 MMX 3DNow!
(C6-2L)
[not released]		296 pins
233MHz (66x3.5)
2.8v/3.3v split		Socket 764KB data (4-way)
64KB instruction (2-way)		10.2 million
0.25µm process
76mm² die
IDT Winchip-3 300 MMX 3DNow!
(C6-2L)
[not released]		296 pins
266MHz (66x4.0)
233MHz (100x2.33)
2.8v/3.3v split		Socket 764KB data (4-way)
64KB instruction (2-way)		10.2 million
0.25µm process
76mm² die
IDT Winchip-3 333 MMX 3DNow!
(C6-2L)
[not released]		296 pins
266MHz (100x2.66)
250MHz (100x2.5)
2.8v/3.3v split		Socket 764KB data (4-way)
64KB instruction (2-way)		10.2 million
0.25µm process
76mm² die
IDT Winchip-4 400 MMX 3DNow!
(C7)
[cancelled]		296 pins
?MHz (?x?)
2.8v/3.3v split		Super 764KB data (4-way)
64KB instruction (2-way)		11.6 million
0.25µm process
95mm² die
IDT Winchip-4 500 MMX 3DNow!
(?)
[cancelled]		296 pins
?MHz (?x?)
1.8v/3.3v split		Super 764KB data (4-way)
64KB instruction (2-way)		11.6 million
0.18µm process
60mm² die
Cyrix
Processors		Natural
State		SocketsL1 Cache
(Associativity)		Transistors
Cx5gx86 200 MMX
(MediaGXm)
January 6, 1998 - {$114}		352 pin BGA
320 pin SPGA
200MHz (66x3.0)
2.5v		Proprietary16KB unified2.4 million
0.5µm process
160mm² die
Cx5gx86 233 MMX
(MediaGXm)
March 18, 1998 - {$81}		320 pin SPGA
233MHz (66x3.5)
2.5v		Proprietary16KB unified2.4 million
0.5µm process
160mm² die
Cx5gx86 266 MMX
(MediaGXm)
October 1998		320 pin SPGA
266MHz (66x4.0)
2.5v		Proprietary16KB unified2.4 million
0.5µm process
160mm² die
6x86MX PR166 MMX
(M2)
Manuf: IBM
May 30, 1997 - {$190}		296 pins
150MHz (60x2.5)
133MHz (66x2.0)
2.9v/3.3v split		Socket 764KB unified (4-way)6.0 million
0.35µm 5M process
197mm² die
6x86MX PR200 MMX
(M2)
Manuf: IBM (0.35µ)
Manuf: NSI (0.30µ)
May 30, 1997 - {$240}		296 pins
166MHz (66x2.5)
150MHz (75x2.0)
2.9v/3.3v split		Socket 764KB unified (4-way)6.0 million
0.35µm 5M process
197mm² die
0.30µm process (2Q 98)
156mm² die
6x86MX PR233 MMX
(M2)
Manuf: IBM (0.35µ)
Manuf: NSI (0.30µ)
May 30, 1997 - {$320}		296 pins
200MHz (66x3.0)
188MHz (75x2.5)
2.9v/3.3v split		Socket 764KB unified (4-way)6.0 million
0.35µm 5M process
197mm² die
0.30µm process (2Q 98)
156mm² die
6x86MX PR266 MMX
(M2) - Very few chips produced.
Manuf: IBM (0.35µ)
Manuf: NSI (0.30µ)
March 19, 1998 - {$180}		296 pins
208MHz (83x2.5)
2.9v/3.3v split		Socket 764KB unified (4-way)6.0 million
0.35µm 5M process
197mm² die
0.30µm process (2Q 98)
156mm² die
M II 233 MMX
(M2)
Manuf: NSI		296 pins
200MHz (66x3.0)
2.9v/3.3v split		Socket 764KB unified (4-way)6.0 million
0.30µm process
156mm² die
M II 266 MMX
(M2)
Manuf: NSI		296 pins
200MHz (66x3.0)
2.9v/3.3v split		Socket 764KB unified (4-way)6.0 million
0.25µm process
88mm² die
M II 300 MMX
(M2)
Manuf: NSI
April 14, 1998 - {$180}		296 pins
233MHz (66x3.5)
225MHz (75x3.0)
2.9v/3.3v split		Socket 764KB unified (4-way)6.0 million
0.30µm process
156mm² die
0.25µm process (1Q 99)
88mm² die
M II 333 MMX
(M2)
Manuf: NSI
June 15, 1998 - {$180}		296 pins
250MHz (100x2.5)
2.9v/3.3v split		Super 764KB unified (4-way)6.0 million
0.30µm process
156mm² die
0.25µm process (1Q 99)
88mm² die
M II 333 MMX
(M2)
Manuf: NSI
March 1999		296 pins
250MHz (83x3.0)
2.9v/3.3v split		Super 764KB unified (4-way)6.0 million
0.25µm process
88mm² die
M II 366 MMX
(M2)
Manuf: NSI
March 1999		296 pins
250MHz (100x2.5)
2.9v/3.3v split		Super 764KB unified (4-way)6.0 million
0.25µm process
88mm² die
M II 400 MMX
(M2)
Manuf: NSI
June 1999		321 pins
285MHz (95x3.0)
2.2v/3.3v split		Super 764KB unified (4-way)6.0 million
0.18µm process
65mm² die
M II 433 MMX
(M2)
Manuf: NSI
June 1999		321 pins
300MHz (100x3.0)
2.2v/3.3v split		Super 764KB unified (4-way)6.0 million
0.18µm process
65mm² die
IBM
Processors		Natural
State		SocketsL1 Cache
(Associativity)		Transistors
6x86MX PR166 MMX
(M2)
May 30, 1997 - {$202}		296 pins
150MHz (60x2.5)
133MHz (66x2.0)
2.9v/3.3v split		Socket 764KB unified (4-way)6.0 million
0.35µm process
197mm² die
6x86MX PR200 MMX
(M2)
May 30, 1997 - {$369}		296 pins
166MHz (66x2.5)
150MHz (75x2.0)
2.9v/3.3v split		Socket 764KB unified (4-way)6.0 million
0.35µm process
197mm² die
0.30µm process (2Q 98)
?mm² die
6x86MX PR233 MMX
(M2)
May 30, 1997 - {$477}		296 pins
200MHz (66x3.0)
188MHz (75x2.5)
166MHz (83x2.0)
2.9v/3.3v split		Socket 764KB unified (4-way)6.0 million
0.35µm process
197mm² die
0.30µm process (2Q 98)
?mm² die
6x86MX PR266 MMX
(M2) - Very few chips produced.
March 19, 1998		296 pins
208MHz (83x2.5)
2.9v/3.3v split		Socket 764KB unified (4-way)6.0 million
0.35µm process
197mm² die
0.30µm process (2Q 98)
?mm² die
6x86MX PR300 MMX
(M2)
May 19, 1998 - {$217}		296 pins
233MHz (66x3.5)
225MHz (75x3.0)
2.9v/3.3v split		Socket 764KB unified (4-way)6.0 million
0.25µm process
119mm² die
6x86MX PR333 MMX
(M2)
May 19, 1998 - {$299}		296 pins
263MHz (75x3.5)
250MHz (83x3.0)
2.9v/3.3v split		Socket 764KB unified (4-way)6.0 million
0.25µm process
119mm² die
Intel
Processors		Natural
State		SocketsL1 Cache
(Associativity)		Transistors
Pentium 166 MMX
(P55C)
January 8, 1997 - {$407}		296 pins
166MHz (66x2.5)
2.8v/3.3v split		Socket 716KB data (4-way)
16KB instruction (4-way)		4.5 million
0.35µm process
141mm² die
Pentium 200 MMX
(P55C)
January 8, 1997 - {$550}		296 pins
200MHz (66x3.0)
2.8v/3.3v split		Socket 716KB data (4-way)
16KB instruction (4-way)		4.5 million
0.35µm process
141mm² die
Pentium 233 MMX
(P55C)
June 2, 1997 - {$594}		296 pins
233MHz (66x3.5)
2.8v/3.3v split		Socket 716KB data (4-way)
16KB instruction (4-way)		4.5 million
0.35µm process
141mm² die
PentiumODPMT 150 MMX
(P54CTB)
March 3, 1997 - {$399}		320 pins
150MHz (60x2.5)
125MHz (50x2.5)
3.3v to 2.8v		Socket 5
Socket 7		16KB data (4-way)
16KB instruction (4-way)		4.5 million
0.35µm process
141mm² die
PentiumODPMT 166 MMX
(P54CTB)
March 3, 1997 - {$499}		320 pins
166MHz (66x2.5)
3.3v to 2.8v		Socket 5
Socket 7		16KB data (4-way)
16KB instruction (4-way)		4.5 million
0.35µm process
141mm² die
PentiumODPMT 180 MMX
(P54CTB)
August 4, 1997 - {$299}		320 pins
180MHz (60x3.0)
3.3v to 2.8v		Socket 5
Socket 7		16KB data (4-way)
16KB instruction (4-way)		4.5 million
0.35µm process
141mm² die
PentiumODPMT 200 MMX
(P54CTB)
August 4, 1997 - {$349}		320 pins
200MHz (66x3.0)
3.3v to 2.8v		Socket 716KB data (4-way)
16KB instruction (4-way)		4.5 million
0.35µm process
141mm² die
Rise
Processors		Natural
State		SocketsL1 Cache
(Associativity)		Transistors
mP6 166 MMX
(?)
February 1999 - {$50}		296 pins
166MHz (83x2.0)
2.8v/3.3v split		Socket 78KB data
8KB instruction		3.6 million
0.25µm process
107mm² die
mP6 233 MMX
(?)
February 1999 - {$60}		296 pins
190MHz (95x2.0)
2.8v/3.3v split		Super 78KB data
8KB instruction		3.6 million
0.25µm process
107mm² die
mP6 266 MMX
(?)
February 1999 - {$70}		296 pins
200MHz (100x2.0)
2.8v/3.3v split		Super 78KB data
8KB instruction		3.6 million
0.25µm process
107mm² die
mP6-II 366 MMX
(?)
[cancelled]		296 pins
250MHz (100x2.5)
2.8v/3.3v split		Super 78KB data (2-way)
8KB instruction (2-way)
256KB on-Die L2 (1-way)
? cacheable		18 million
0.25µm process
?mm² die
mP6-II 380 MMX
(?)
[cancelled]		296 pins
285MHz (95x3.0)
2.0v/3.3v split		Super 78KB data (2-way)
8KB instruction (2-way)
256KB on-Die L2 (1-way)
? cacheable		18 million
0.18µm process
105mm² die
mP6-II 400 MMX
(?)
[cancelled]		296 pins
300MHz (100x3.0)
2.0v/3.3v split		Super 78KB data (2-way)
8KB instruction (2-way)
256KB on-Die L2 (1-way)
? cacheable		18 million
0.18µm process
105mm² die
mP6-II 466 MMX
(?)
[cancelled]		296 pins
350MHz (100x3.5)
2.0v/3.3v split		Super 78KB data (2-way)
8KB instruction (2-way)
256KB on-Die L2 (1-way)
? cacheable		18 million
0.18µm process
105mm² die


Pentium Pro (P6)
Intel
Processors		Natural
State		SocketsL1 Cache
(Associativity)		Transistors
Pentium Pro 133
(P6)
[engineering sample only]		387 pins
133MHz (66x2.0)
3.1v		Socket 88KB data (2-way)
8KB instruction (4-way)
256KB on-Chip unified L2 (4-way)
* 64GB cacheable		5.5 million
0.6µm process
306mm² die
15.5 million L2 {0.6µm - 202mm²}
Pentium Pro 150
(P6)
November 1, 1995 - {$974}		387 pins
150MHz (60x2.5)
3.1v		Socket 88KB data (2-way)
8KB instruction (4-way)
256KB on-Chip unified L2 (4-way)
* 64GB cacheable		5.5 million
0.6µm process
306mm² die
15.5 million L2 {0.6µm - 202mm²}
Pentium Pro 166
(P6)
November 1, 1995 - {$1682}		387 pins
166MHz (66x2.5)
3.3v		Socket 88KB data (2-way)
8KB instruction (4-way)
512KB on-Chip unified L2 (4-way)
* 64GB cacheable		5.5 million
0.35µm process
195mm² die
31 million L2 {0.35µm - 242mm²}
Pentium Pro 180
(P6)
November 1, 1995 - {$1075}		387 pins
180MHz (60x3.0)
3.3v		Socket 88KB data (2-way)
8KB instruction (4-way)
256KB on-Chip unified L2 (4-way)
* 64GB cacheable		5.5 million
0.35µm process
195mm² die
15.5 million L2 {0.6µm - 202mm²}
Pentium Pro 200
(P6)
November 1, 1995 - {$1325} (256KB)
November 1, 1995 - {$1989} (512KB)
August 18, 1997 - {$2650} (1MB)		387 pins
200MHz (66x3.0)
3.3v or 3.5v		Socket 88KB data (2-way)
8KB instruction (4-way)
256KB or
512KB or
1MB on-Chip unified L2 (4-way)
* 64GB cacheable		5.5 million
0.35µm process
195mm² die
15.5 million L2 {0.6µm - 202mm²} (256KB)
31 million L2 {0.35µm - 242mm²} (512KB)
62 million L2 {0.35µm - (2) 242mm²} (1MB)
Pentium II OverDrive 333 MMX
(P6T)
August 10, 1998 - {$599}		387 pins
300MHz (60x5.0)
333MHz (66x5.0)
2.0v/2.5v/3.3v split		Socket 816KB data (4-way)
16KB instruction (4-way)
512KB on-Die unified L2 (4-way)
* 64GB cacheable		? million
0.25µm process
?mm² die


Pentium II/III (Slot 1)
Intel
Processors		Natural
State		SocketsL1 Cache
(Associativity)		Transistors
Pentium II 233 MMX
(Klamath)
May 7, 1997 - {$636}		528 pins (242 pin SEC)
233MHz (66x3.5)
2.8v/3.3v split		Slot 116KB data (4-way)
16KB instruction (4-way)
512KB unified L2 (1/2 speed) (4-way)
* 512MB cacheable		7.5 million
0.35µm process
203mm² die
Pentium II 266 MMX
(Klamath)
May 7, 1997 - {$775}		528 pins (242 pin SEC)
266MHz (66x4.0)
2.8v/3.3v split		Slot 116KB data (4-way)
16KB instruction (4-way)
512KB unified L2 (1/2 speed) (4-way)
* 512MB cacheable		7.5 million
0.35µm process
203mm² die
Pentium II 300 MMX
(Klamath)
May 7, 1997 - {$1981}		528 pins (242 pin SEC)
300MHz (66x4.5)
2.8v/3.3v split		Slot 116KB data (4-way)
16KB instruction (4-way)
512KB unified L2 (1/2 speed) (4-way)
* 512MB cacheable		7.5 million
0.35µm process
203mm² die
Pentium II 266 MMX
(Deschutes)
September 1, 1998 - {$159}		528 pins (242 pin SEC)
266MHz (66x4.0)
2.0v/3.3v split		Slot 116KB data (4-way)
16KB instruction (4-way)
512KB unified L2 (1/2 speed) (4-way)
* 4GB cacheable		7.5 million
0.25µm process
131mm² die
118mm² die (Aug 98)
Pentium II 300 MMX
(Deschutes)
September 1, 1998 - {$192}		528 pins (242 pin SEC)
300MHz (66x4.5)
2.0v/3.3v split		Slot 116KB data (4-way)
16KB instruction (4-way)
512KB unified L2 (1/2 speed) (4-way)
* 4GB cacheable		7.5 million
0.25µm process
131mm² die
118mm² die (Aug 98)
Pentium II 333 MMX
(Deschutes)
January 26, 1998 - {$722}		528 pins (242 pin SEC)
333MHz (66x5.0)
2.0v/3.3v split		Slot 116KB data (4-way)
16KB instruction (4-way)
512KB unified L2 (1/2 speed) (4-way)
* dA0 512MB cacheable
* dA1 4GB cacheable
* dB0 4GB cacheable		7.5 million
0.25µm process
131mm² die
118mm² die (Aug 98)
Pentium II 350 MMX
(Deschutes)
April 15, 1998 - {$621}		528 pins (242 pin SEC)
350MHz (100x3.5)
2.0v/3.3v split		Slot 116KB data (4-way)
16KB instruction (4-way)
512KB unified L2 (1/2 speed) (4-way)
* 4GB cacheable		7.5 million
0.25µm process
131mm² die
118mm² die (Aug 98)
Pentium II 400 MMX
(Deschutes)
April 15, 1998 - {$824}		528 pins (242 pin SEC)
400MHz (100x4.0)
2.0v/3.3v split		Slot 116KB data (4-way)
16KB instruction (4-way)
512KB unified L2 (1/2 speed) (4-way)
* 4GB cacheable		7.5 million
0.25µm process
131mm² die
118mm² die (Aug 98)
Pentium II 450 MMX
(Deschutes)
August 24, 1998 - {$669}		528 pins (242 pin SEC)
450MHz (100x4.5)
2.0v/3.3v split		Slot 116KB data (4-way)
16KB instruction (4-way)
512KB unified L2 (1/2 speed) (4-way)
* 4GB cacheable		7.5 million
0.25µm process
118mm² die
Pentium III 450 MMX SSE
(Katmai)
February 26, 1999 - {$496}		570 pins (242 pin SEC)
450MHz (100x4.5)
2.0v/3.3v split		Slot 116KB data (4-way)
16KB instruction (4-way)
512KB unified L2 (1/2 speed) (4-way)
* 4GB cacheable		9.5 million
0.25µm process
123mm² die
Pentium III 500 MMX SSE
(Katmai)
February 26, 1999 - {$696}		570 pins (242 pin SEC)
500MHz (100x5.0)
2.0v/3.3v split		Slot 116KB data (4-way)
16KB instruction (4-way)
512KB unified L2 (1/2 speed) (4-way)
* 4GB cacheable		9.5 million
0.25µm process
123mm² die
Pentium III 533B MMX SSE
(Katmai)
September 27, 1999 - {$369}		570 pins (242 pin SEC)
533MHz (133x4.0)
2.0v/3.3v split		Slot 116KB data (4-way)
16KB instruction (4-way)
512KB unified L2 (1/2 speed) (4-way)
* 4GB cacheable		9.5 million
0.25µm process
123mm² die
Pentium III 550 MMX SSE
(Katmai)
May 17, 1999 - {$744}		570 pins (242 pin SEC)
550MHz (100x5.5)
2.0v/3.3v split		Slot 116KB data (4-way)
16KB instruction (4-way)
512KB unified L2 (1/2 speed) (4-way)
* 4GB cacheable		9.5 million
0.25µm process
123mm² die
Pentium III 600 MMX SSE
(Katmai)
August 2, 1999 - {$669}		570 pins (242 pin SEC)
600MHz (100x6.0)
2.05v/3.3v split		Slot 116KB data (4-way)
16KB instruction (4-way)
512KB unified L2 (1/2 speed) (4-way)
* 4GB cacheable		9.5 million
0.25µm process
123mm² die
Pentium III 600B MMX SSE
(Katmai)
September 27, 1999 - {$615}		570 pins (242 pin SEC)
600MHz (133x4.5)
2.05v/3.3v split		Slot 116KB data (4-way)
16KB instruction (4-way)
512KB unified L2 (1/2 speed) (4-way)
* 4GB cacheable		9.5 million
0.25µm process
123mm² die
Pentium III 533EB MMX SSE
(Coppermine)
October 25, 1999 - {$305}		495 pins (242 pin SEC)
533MHz (133x4.0)
1.65v		Slot 116KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
Pentium III 550E MMX SSE
(Coppermine)
March 1, 2000		495 pins (242 pin SEC)
550MHz (100x5.5)
1.65v		Slot 116KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
Pentium III 600E MMX SSE
(Coppermine)
October 25, 1999 - {$455}		495 pins (242 pin SEC)
600MHz (100x6.0)
1.65v		Slot 116KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
90mm² die (Jul 00)
Pentium III 600EB MMX SSE
(Coppermine)
October 25, 1999 - {$455}		495 pins (242 pin SEC)
600MHz (133x4.5)
1.65v		Slot 116KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
90mm² die (Jul 00)
Pentium III 650 MMX SSE
(Coppermine)
October 25, 1999 - {$583}		495 pins (242 pin SEC)
650MHz (100x6.5)
1.65v		Slot 116KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
90mm² die (Jul 00)
Pentium III 667 MMX SSE
(Coppermine)
October 25, 1999 - {$605}		495 pins (242 pin SEC)
666MHz (133x5.0)
1.65v		Slot 116KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
90mm² die (Jul 00)
Pentium III 700 MMX SSE
(Coppermine)
October 25, 1999 - {$754}		495 pins (242 pin SEC)
700MHz (100x7.0)
1.65v		Slot 116KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
90mm² die (Jul 00)
Pentium III 733 MMX SSE
(Coppermine)
October 25, 1999 - {$776}		495 pins (242 pin SEC)
733MHz (133x5.5)
1.65v		Slot 116KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
90mm² die (Jul 00)
Pentium III 750 MMX SSE
(Coppermine)
December 20, 1999 - {$803}		495 pins (242 pin SEC)
750MHz (100x7.5)
1.65v		Slot 116KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
90mm² die (Jul 00)
Pentium III 800 MMX SSE
(Coppermine)
December 20, 1999 - {$851}		495 pins (242 pin SEC)
800MHz (100x8.0)
1.65v		Slot 116KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
90mm² die (Jul 00)
Pentium III 800EB MMX SSE
(Coppermine)
December 20, 1999 - {$851}		495 pins (242 pin SEC)
800MHz (133x6.0)
1.65v		Slot 116KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
90mm² die (Jul 00)
Pentium III 850 MMX SSE
(Coppermine)
March 20, 2000 - {$765}		495 pins (242 pin SEC)
850MHz (100x8.5)
1.65v		Slot 116KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
105mm² die
90mm² die (Jul 00)
Pentium III 866 MMX SSE
(Coppermine)
March 20, 2000 - {$776}		495 pins (242 pin SEC)
866MHz (133x6.5)
1.65v		Slot 116KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
105mm² die
90mm² die (Jul 00)
Pentium III 933 MMX SSE
(Coppermine)
May 24, 2000 - {$744}		495 pins (242 pin SEC)
933MHz (133x7.0)
1.7v		Slot 116KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
105mm² die
90mm² die (Jul 00)
Pentium III 1.0B MMX SSE
(Coppermine)
March 8, 2000 - {$990}		495 pins (242 pin SEC)
1000MHz (133x7.5)
1.7v		Slot 116KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
105mm² die
90mm² die (Jul 00)
Pentium III 1.0G MMX SSE
(Coppermine)
July 31, 2000		495 pins (242 pin SEC)
1000MHz (100x10.0)
1.7v		Slot 116KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
90mm² die
Pentium III 1.13G MMX SSE
(Coppermine)
July 31, 2000 - {$990} [recalled in Aug]		495 pins (242 pin SEC)
1133MHz (133x8.5)
1.8v		Slot 116KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
90mm² die
Celeron 266 MMX
(Covington)
April 15, 1998 - {$155}		528 pins (242 pin SEPP)
266MHz (66x4.0)
2.0v		Slot 116KB data (4-way)
16KB instruction (4-way)		7.5 million
0.25µm process
131mm² die
Celeron 300 MMX
(Covington)
June 8, 1998 - {$159}		528 pins (242 pin SEPP)
300MHz (66x4.5)
2.0v		Slot 116KB data (4-way)
16KB instruction (4-way)		7.5 million
0.25µm process
131mm² die
Celeron 300A MMX
(Mendocino)
August 24, 1998 - {$149}		528 pins (242 pin SEPP)
300MHz (66x4.5)
2.0v		Slot 116KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		19 million
0.25µm process
154mm² die
Celeron 333 MMX
(Mendocino)
August 24, 1998 - {$192}		528 pins (242 pin SEPP)
333MHz (66x5.0)
2.0v		Slot 116KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		19 million
0.25µm process
154mm² die
Celeron 366 MMX
(Mendocino)
January 4, 1999 - {$131}		528 pins (242 pin SEPP)
366MHz (66x5.5)
2.0v		Slot 116KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		19 million
0.25µm process
154mm² die
Celeron 400 MMX
(Mendocino)
January 4, 1999 - {$166}		528 pins (242 pin SEPP)
400MHz (66x6.0)
2.0v		Slot 116KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		19 million
0.25µm process
154mm² die
Celeron 433 MMX
(Mendocino)
March 22, 1999 - {$177}		528 pins (242 pin SEPP)
433MHz (66x6.5)
2.0v		Slot 116KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		19 million
0.25µm process
154mm² die


Pentium II/III Xeon (Slot 2)
Intel
Processors		Natural
State		SocketsL1 Cache
(Associativity)		Transistors
Pentium II Xeon 400 MMX
(Drake)
June 29, 1998 - {$1124} (512KB)
June 29, 1998 - {$2836} (1MB)		528 pins (330 pin SEC)
400MHz (100x4.0)
2.0v/2.5v split		Slot 216KB data (4-way)
16KB instruction (4-way)
512KB or
1MB unified L2 (4-way)
* 64GB cacheable		7.5 million
0.25µm process
131mm² die
118mm² die (Aug 98)
Pentium II Xeon 450 MMX
(Drake)
October 6, 1998 - {$824} (512KB)
January 5, 1999 - {$1980} (1MB)
January 5, 1999 - {$3692} (2MB)		528 pins (330 pin SEC)
450MHz (100x4.5)
2.0v/2.7v split		Slot 216KB data (4-way)
16KB instruction (4-way)
512KB or
1MB or
2MB unified L2 (4-way)
* 64GB cacheable		7.5 million
0.25µm process
118mm² die
Pentium III Xeon 500 MMX SSE
(Tanner)
March 17, 1999 - {$931} (512KB)
March 17, 1999 - {$1980} (1MB)
March 17, 1999 - {$3692} (2MB)		570 pins (330 pin SEC)
500MHz (100x5.0)
2.0v/2.7v split
2.0v/2.0v split (2MB L2)		Slot 216KB data (4-way)
16KB instruction (4-way)
512KB or
1MB or
2MB unified L2 (4-way)
* 64GB cacheable		9.5 million
0.25µm process
123mm² die
Pentium III Xeon 550 MMX SSE
(Tanner - 2-way)
April 7, 1999 - {$1059}		570 pins (330 pin SEC)
550MHz (100x5.5)
2.0v/2.0v split		Slot 216KB data (4-way)
16KB instruction (4-way)
512KB unified L2 (4-way)
* 64GB cacheable		9.5 million
0.25µm process
123mm² die
Pentium III Xeon 550 MMX SSE
(Tanner)
August 23, 1999 - {$931} (512KB)
August 23, 1999 - {$1980} (1MB)
August 23, 1999 - {$3692} (2MB)		570 pins (330 pin SEC)
550MHz (100x5.5)
2.0v/2.0v split		Slot 216KB data (4-way)
16KB instruction (4-way)
512KB or
1MB or
2MB unified L2 (4-way)
* 64GB cacheable		9.5 million
0.25µm process
123mm² die
Pentium III Xeon 600 MMX SSE
(Cascades)
October 25, 1999 - {$505}		495 pins (330 pin SEC)
600MHz (133x4.5)
2.8v or 5.0v or 12.0v		Slot 216KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 64GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
Pentium III Xeon 667 MMX SSE
(Cascades)
October 25, 1999 - {$655}		495 pins (330 pin SEC)
666MHz (133x5.0)
2.8v or 5.0v or 12.0v		Slot 216KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 64GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
Pentium III Xeon 700 MMX SSE
(Cascades)
May 22, 2000 (1MB) - {$1177}
May 22, 2000 (2MB) - {$1980}		495 pins (330 pin SEC)
700MHz (100x7.0)
2.8v or 5.0v or 12.0v		Slot 216KB data (4-way)
16KB instruction (4-way)
1MB or
2MB on-Die unified L2 (8-way)
* 64GB cacheable		140 million
0.18µm process
300+mm² die
Pentium III Xeon 733 MMX SSE
(Cascades)
October 25, 1999 - {$826}		495 pins (330 pin SEC)
733MHz (133x5.5)
2.8v or 5.0v or 12.0v		Slot 216KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 64GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
100mm² die (Jul 00)
Pentium III Xeon 800 MMX SSE
(Cascades)
January 12, 2000 - {$901}		495 pins (330 pin SEC)
800MHz (133x6.0)
2.8v or 5.0v or 12.0v		Slot 216KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 64GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
100mm² die (Jul 00)
Pentium III Xeon 866 MMX SSE
(Cascades)
March 13, 2000		495 pins (330 pin SEC)
866MHz (133x6.5)
2.8v or 5.0v or 12.0v		Slot 216KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 64GB cacheable		28 million
0.18µm process
105mm² die
100mm² die (Jul 00)
Pentium III Xeon 900 MMX SSE
(Cascades)
March 20, 2001 - {$3692}		495 pins (330 pin SEC)
900MHz (100x9.0)
2.8v or 5.0v or 12.0v		Slot 216KB data (4-way)
16KB instruction (4-way)
2MB on-Die unified L2 (8-way)
* 64GB cacheable		140 million
0.18µm process
300+mm² die
Pentium III Xeon 933 MMX SSE
(Cascades)
May 24, 2000 - {$794}		495 pins (330 pin SEC)
933MHz (133x7.0)
2.8v or 5.0v or 12.0v		Slot 216KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 64GB cacheable		28 million
0.18µm process
105mm² die
100mm² die (Jul 00)
Pentium III Xeon 1G MMX SSE
(Cascades)
August 22, 2000 - {$719}		495 pins (330 pin SEC)
1000MHz (133x7.5)
2.8v or 5.0v or 12.0v		Slot 216KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 64GB cacheable		28 million
0.18µm process
100mm² die


Socket 370
Cyrix
Processors		Natural
State		SocketsL1 Cache
(Associativity)		Transistors
M3 600 MMX
(Mojave)
[cancelled]		370 pins
?MHz (133x?)
1.8v		Socket 37016KB data (4-way)
16KB instruction (4-way)
256KB on-Die L2 (8-way)
* ?GB cacheable		25 million
0.21µm process
110mm² die
Intel
Processors		Natural
State		SocketsL1 Cache
(Associativity)		Transistors
Celeron 300A MMX
(Mendocino)
November 30, 1998 - {$70}		370 pins
300MHz (66x4.5)
2.0v		Socket 37016KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		19 million
0.25µm process
154mm² die
Celeron 333 MMX
(Mendocino)
November 30, 1998 - {$87}		370 pins
333MHz (66x5.0)
2.0v		Socket 37016KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		19 million
0.25µm process
154mm² die
Celeron 366 MMX
(Mendocino)
January 4, 1999 - {$123}		370 pins
366MHz (66x5.5)
2.0v		Socket 37016KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		19 million
0.25µm process
154mm² die
Celeron 400 MMX
(Mendocino)
January 4, 1999 - {$158}		370 pins
400MHz (66x6.0)
2.0v		Socket 37016KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		19 million
0.25µm process
154mm² die
Celeron 433 MMX
(Mendocino)
March 22, 1999 - {$169}		370 pins
433MHz (66x6.5)
2.0v		Socket 37016KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		19 million
0.25µm process
154mm² die
Celeron 466 MMX
(Mendocino)
April 26, 1999 - {$169}		370 pins
466MHz (66x7.0)
2.0v		Socket 37016KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		19 million
0.25µm process
154mm² die
Celeron 500 MMX
(Mendocino)
August 2, 1999 - {$167}		370 pins
500MHz (66x7.5)
2.0v		Socket 37016KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		19 million
0.25µm process
154mm² die
Celeron 533 MMX
(Mendocino)
January 4, 2000 - {$167}		370 pins
533MHz (66x8.0)
2.0v		Socket 37016KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		19 million
0.25µm process
154mm² die
Celeron 500A MMX SSE
(Coppermine-128)
March 29, 2000 [may not exist]		370 pins
500MHz (66x7.5)
1.5v or 1.7v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		28 million
0.18µm process
105mm² die
Celeron 533A MMX SSE
(Coppermine-128)
March 29, 2000		370 pins
533MHz (66x8.0)
1.5v or 1.7v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		28 million
0.18µm process
105mm² die
90mm² die (Jun 00)
Celeron 566 MMX SSE
(Coppermine-128)
March 29, 2000 - {$167}		370 pins
566MHz (66x8.5)
1.5v or 1.7v or 1.75v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		28 million
0.18µm process
105mm² die
90mm² die (Jun 00)
Celeron 600 MMX SSE
(Coppermine-128)
March 29, 2000 - {$181}		370 pins
600MHz (66x9.0)
1.5v or 1.7v or 1.75v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		28 million
0.18µm process
105mm² die
90mm² die (Jun 00)
Celeron 633 MMX SSE
(Coppermine-128)
June 26, 2000 - {$138}		370 pins
633MHz (66x9.5)
1.65v or 1.7v or 1.75v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		28 million
0.18µm process
105mm² die
90mm² die (Jun 00)
Celeron 667 MMX SSE
(Coppermine-128)
June 26, 2000 - {$170}		370 pins
666MHz (66x10.0)
1.65v or 1.7v or 1.75v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		28 million
0.18µm process
105mm² die
90mm² die (Jun 00)
Celeron 700 MMX SSE
(Coppermine-128)
June 26, 2000 - {$192}		370 pins
700MHz (66x10.5)
1.65v or 1.7v or 1.75v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		28 million
0.18µm process
105mm² die
90mm² die (Jun 00)
Celeron 733 MMX SSE
(Coppermine-128)
November 13, 2000 - {$112}		370 pins
733MHz (66x11.0)
1.65v or 1.7v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		28 million
0.18µm process
90mm² die
95mm² die (Jul 01)
Celeron 766 MMX SSE
(Coppermine-128)
November 13, 2000 - {$170}		370 pins
766MHz (66x11.5)
1.65v or 1.7v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		28 million
0.18µm process
90mm² die
Celeron 800 MMX SSE
(Coppermine-128)
January 3, 2001 - {$170}		370 pins
800MHz (100x8.0)
1.65v or 1.7v or 1.75v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		28 million
0.18µm process
90mm² die
95mm² die (Jul 01)
Celeron 850 MMX SSE
(Coppermine-128)
April 9, 2001 - {$138}		370 pins
850MHz (100x8.5)
1.65v or 1.7v or 1.75v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		28 million
0.18µm process
90mm² die
95mm² die (Jul 01)
Celeron 900 MMX SSE
(Coppermine-128)
July 2, 2001 - {$103}		370 pins
900MHz (100x9.0)
1.75v		Socket 370
(FC-PGA)
(FC-PGA2)		16KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		28 million
0.18µm process
95mm² die
Celeron 950 MMX SSE
(Coppermine-128)
August 31, 2001 - {$74}		370 pins
950MHz (100x9.5)
1.75v		Socket 370
(FC-PGA)
(FC-PGA2)		16KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		28 million
0.18µm process
95mm² die
Celeron 1.0G MMX SSE
(Coppermine-128)
August 31, 2001 - {$89}		370 pins
1000MHz (100x10.0)
1.75v		Socket 370
(FC-PGA)
(FC-PGA2)		16KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		28 million
0.18µm process
95mm² die
Celeron 1.1G MMX SSE
(Coppermine-128)
August 31, 2001 - {$103}		370 pins
1100MHz (100x11.0)
1.75v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
128KB on-Die unified L2 (4-way)
* 4GB cacheable		28 million
0.18µm process
95mm² die
Celeron 900A MMX SSE
(Tualatin)
May 15, 2002		370 pins
900MHz (100x9.0)
1.475v		Socket 370
(FC-PGA2)
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		44 million
0.13µm process
80mm² die
Celeron 1.0A MMX SSE
(Tualatin)
January 3, 2002		370 pins
1000MHz (100x10.0)
1.475v or 1.5v		Socket 370
(FC-PGA2)
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		44 million
0.13µm process
80mm² die
Celeron 1.1A MMX SSE
(Tualatin)
January 3, 2002		370 pins
1100MHz (100x11.0)
1.475v or 1.5v		Socket 370
(FC-PGA2)
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		44 million
0.13µm process
80mm² die
Celeron 1.2G MMX SSE
(Tualatin)
October 2, 2001 - {$103}		370 pins
1200MHz (100x12.0)
1.475v or 1.5v		Socket 370
(FC-PGA2)
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		44 million
0.13µm process
80mm² die
Celeron 1.3G MMX SSE
(Tualatin)
January 3, 2002 - {$118}		370 pins
1300MHz (100x13.0)
1.5v		Socket 370
(FC-PGA2)
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		44 million
0.13µm process
80mm² die
Celeron 1.4G MMX SSE
(Tualatin)
May 15, 2002 - {$89}		370 pins
1400MHz (100x14.0)
1.5v		Socket 370
(FC-PGA2)
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		44 million
0.13µm process
80mm² die
Pentium III 500E MMX SSE
(Coppermine)
October 25, 1999 - {$239}		370 pins
500MHz (100x5.0)
1.6v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
Pentium III 533EB MMX SSE
(Coppermine)
March 1, 2000		370 pins
533MHz (133x4.0)
1.65v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
Pentium III 550E MMX SSE
(Coppermine)
October 25, 1999 - {$368}		370 pins
550MHz (100x5.5)
1.6v or 1.65v or 1.7v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
90mm² die (Jul 00)
Pentium III 600E MMX SSE
(Coppermine)
March 1, 2000		370 pins
600MHz (100x6.0)
1.65v or 1.7v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
90mm² die (Jul 00)
95mm² die (May 01)
Pentium III 600EB MMX SSE
(Coppermine)
March 1, 2000		370 pins
600MHz (133x4.5)
1.65v or 1.7v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
90mm² die (Jul 00)
Pentium III 650 MMX SSE
(Coppermine)
March 1, 2000		370 pins
650MHz (100x6.5)
1.65v or 1.7v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
90mm² die (Jul 00)
Pentium III 667 MMX SSE
(Coppermine)
March 1, 2000		370 pins
666MHz (133x5.0)
1.65v or 1.7v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
90mm² die (Jul 00)
Pentium III 700 MMX SSE
(Coppermine)
March 1, 2000		370 pins
700MHz (100x7.0)
1.65v or 1.7v or 1.75v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
90mm² die (Jul 00)
95mm² die (May 01)
Pentium III 733 MMX SSE
(Coppermine)
March 1, 2000		370 pins
733MHz (133x5.5)
1.65v or 1.7v or 1.75v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
90mm² die (Jul 00)
Pentium III 750 MMX SSE
(Coppermine)
March 1, 2000		370 pins
750MHz (100x7.5)
1.65v or 1.7v or 1.75v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
90mm² die (Jul 00)
95mm² die (May 01)
Pentium III 800E MMX SSE
(Coppermine)
March 1, 2000		370 pins
800MHz (100x8.0)
1.65v or 1.7v or 1.75v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
90mm² die (Jul 00)
Pentium III 800EB MMX SSE
(Coppermine)
March 1, 2000		370 pins
800MHz (133x6.0)
1.65v or 1.7v or 1.75v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
106mm² die
105mm² die (Mar 00)
90mm² die (Jul 00)
95mm² die (May 01)
Pentium III 850 MMX SSE
(Coppermine)
March 20, 2000 - {$765}		370 pins
850MHz (100x8.5)
1.65v or 1.7v or 1.75v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
105mm² die
90mm² die (Jul 00)
Pentium III 866 MMX SSE
(Coppermine)
March 20, 2000 - {$776}		370 pins
866MHz (133x6.5)
1.65v or 1.7v or 1.75v		Socket 370
(FC-PGA)
(FC-PGA2)		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
105mm² die
90mm² die (Jul 00)
95mm² die (May 01)
Pentium III 900 MMX SSE
(Coppermine)
October, 2000		370 pins
900MHz (100x9.0)
1.7v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
90mm² die
95mm² die (May 01)
Pentium III 933 MMX SSE
(Coppermine)
May 24, 2000 - {$744}		370 pins
933MHz (133x7.0)
1.65v or 1.7v or 1.75v		Socket 370
(FC-PGA)
(FC-PGA2)		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
105mm² die
90mm² die (Jul 00)
95mm² die (May 01)
Pentium III 1.0G MMX SSE
(Coppermine)
June, 2001		370 pins
1000MHz (100x10.0)
1.75v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
95mm² die
Pentium III 1.0B MMX SSE
(Coppermine)
January, 2001		370 pins
1000MHz (133x7.5)
1.7v or 1.75v or 1.76v		Socket 370
(FC-PGA)
(FC-PGA2)		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
90mm² die
95mm² die (May 01)
Pentium III 1.1G MMX SSE
(Coppermine)
June, 2001		370 pins
1100MHz (100x11.0)
1.75v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
95mm² die
Pentium III 1.13G MMX SSE
(Coppermine)
June, 2001		370 pins
1133MHz (133x8.5)
1.75v		Socket 370
(FC-PGA)		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
95mm² die
Pentium III 866 MMX SSE
(Coppermine-T)
June, 2001		370 pins
866MHz (133x6.5)
1.75v		Socket 370
(FC-PGA)
1.5v AGTL+
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
95mm² die
Pentium III 933 MMX SSE
(Coppermine-T)
June, 2001		370 pins
933MHz (133x7.0)
1.75v		Socket 370
(FC-PGA)
1.5v AGTL+
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
95mm² die
Pentium III 1.0B MMX SSE
(Coppermine-T)
June, 2001		370 pins
1000MHz (133x7.5)
1.75v		Socket 370
(FC-PGA2)
1.5v AGTL+
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
95mm² die
Pentium III 1.13G MMX SSE
(Coppermine-T)
June, 2001		370 pins
1133MHz (133x8.5)
1.75v		Socket 370
(FC-PGA2)
1.5v AGTL+
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable		28 million
0.18µm process
95mm² die
Pentium III 1.0B MMX SSE
(Tualatin)
July 18, 2001		370 pins
1000MHz (133x7.5)
1.475v		Socket 370
(FC-PGA2)
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 64GB cacheable		44 million
0.13µm process
80mm² die
Pentium III 1.13A MMX SSE
(Tualatin)
July, 2001		370 pins
1133MHz (133x8.5)
1.475v or 1.5v		Socket 370
(FC-PGA2)
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 64GB cacheable		44 million
0.13µm process
80mm² die
Pentium III 1.2G MMX SSE
(Tualatin)
July, 2001		370 pins
1200MHz (133x9.0)
1.475v or 1.5v		Socket 370
(FC-PGA2)
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 64GB cacheable		44 million
0.13µm process
80mm² die
Pentium III 1.33G MMX SSE
(Tualatin)
December, 2001		370 pins
1333MHz (133x10.0)
1.5v		Socket 370
(FC-PGA2)
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 64GB cacheable		44 million
0.13µm process
80mm² die
Pentium III 1.4G MMX SSE
(Tualatin)
June, 2002		370 pins
1400MHz (133x10.5)
1.5v		Socket 370
(FC-PGA2)
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
256KB on-Die unified L2 (8-way)
* 64GB cacheable		44 million
0.13µm process
80mm² die
Pentium III-S 700 MMX SSE
(Tualatin)
November 13, 2001		370 pins
700MHz (100x7.0)
1.1v		Socket 370
(FC-PGA2)
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		44 million
0.13µm process
80mm² die
Pentium III-S 800 MMX SSE
(Tualatin)
March 19, 2002		479 balls
800MHz (133x6.0)
1.15v		Proprietary
µFCBGA
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		44 million
0.13µm process
80mm² die
Pentium III-S 900 MMX SSE
(Tualatin)
[not released]		370 pins
900MHz (100x9.0)
?v		Socket 370
(FC-PGA2)
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		44 million
0.13µm process
80mm² die
Pentium III-S 933 MMX SSE
(Tualatin)
[not released]		370 pins
933MHz (133x7.0)
1.1v		Socket 370
(FC-PGA2)
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		44 million
0.13µm process
80mm² die
Pentium III-S 1.13G MMX SSE
(Tualatin)
June 21, 2001		370 pins
1133MHz (133x8.5)
1.45v		Socket 370
(FC-PGA2)
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		44 million
0.13µm process
80mm² die
Pentium III-S 1.26G MMX SSE
(Tualatin)
July 18, 2001		370 pins
1266MHz (133x9.5)
1.45v		Socket 370
(FC-PGA2)
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		44 million
0.13µm process
80mm² die
Pentium III-S 1.4G MMX SSE
(Tualatin)
January 8, 2002 - {$315}		370 pins
1400MHz (133x10.5)
1.45v		Socket 370
(FC-PGA2)
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		44 million
0.13µm process
80mm² die
Pentium III-S 1.53G MMX SSE
(Tualatin)
[not released]		370 pins
1533MHz (133x11.5)
1.45v		Socket 370
(FC-PGA2)
1.25v AGTL		16KB data (4-way)
16KB instruction (4-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable		44 million
0.13µm process
80mm² die
Rise
Processors		Natural
State		SocketsL1 Cache
(Associativity)		Transistors
? MMX SSE
(Tiger)
[cancelled]		370 pins
?MHz (100x?)
1.8v/2.5v split		Socket 370?KB data
?KB instruction
?KB on-Die L2
? cacheable		? million
0.18µm process
?mm² die
VIA
Processors		Natural
State		SocketsL1 Cache
(Associativity)		Transistors
Cyrix III PR433 MMX 3DNow!
(Joshua)
February 22, 2000 [cancelled]		370 pins
333MHz (66x5.0)
2.2v		Socket 37064KB unified (4-way)
256KB on-Die L2 (8-way exclusive)
* 4GB cacheable		22 million
0.18µm process
?mm² die
Cyrix III PR466 MMX 3DNow!
(Joshua)
February 22, 2000 [cancelled]		370 pins
366MHz (66x5.5)
2.2v		Socket 37064KB unified (4-way)
256KB on-Die L2 (8-way exclusive)
* 4GB cacheable		22 million
0.18µm process
?mm² die
Cyrix III PR500 MMX 3DNow!
(Joshua)
February 22, 2000 - {$84} [cancelled]		370 pins
400MHz (133x3.0)
2.2v		Socket 37064KB unified (4-way)
256KB on-Die L2 (8-way exclusive)
* 4GB cacheable		22 million
0.18µm process
?mm² die
Cyrix III PR533 MMX 3DNow!
(Joshua)
February 22, 2000 - {$99} [cancelled]		370 pins
450MHz (100x4.5)
434MHz (124x3.5)
2.2v		Socket 37064KB unified (4-way)
256KB on-Die L2 (8-way exclusive)
* 4GB cacheable		22 million
0.18µm process
?mm² die
Cyrix III 500 MMX 3DNow!
(Samuel/C5)
June 6, 2000		370 pins
500MHz (100x5.0)
1.9v or 2.0v		Socket 37064KB data (4-way)
64KB instruction (2-way)		11.3 million
0.18µm process
75mm² die
Cyrix III 533 MMX 3DNow!
(Samuel/C5)
June 6, 2000 - {$75}		370 pins
533MHz (133x4.0)
1.9v or 2.0v		Socket 37064KB data (4-way)
64KB instruction (2-way)		11.3 million
0.18µm process
75mm² die
Cyrix III 550 MMX 3DNow!
(Samuel/C5)
June 6, 2000		370 pins
550MHz (100x5.5)
1.9v or 2.0v		Socket 37064KB data (4-way)
64KB instruction (2-way)		11.3 million
0.18µm process
75mm² die
Cyrix III 600 MMX 3DNow!
(Samuel/C5)
June 6, 2000		370 pins
600MHz (100x6.0)
1.9v or 2.0v		Socket 37064KB data (4-way)
64KB instruction (2-way)		11.3 million
0.18µm process
75mm² die
Cyrix III 650 MMX 3DNow!
(Samuel/C5)
November 30, 2000 - {$55}		370 pins
650MHz (100x6.5)
1.9v or 2.0v		Socket 37064KB data (4-way)
64KB instruction (2-way)		11.3 million
0.18µm process
75mm² die
Cyrix III 667 MMX 3DNow!
(Samuel/C5)
November 30, 2000 - {$60}		370 pins
666MHz (133x5.0)
1.9v or 2.0v		Socket 37064KB data (4-way)
64KB instruction (2-way)		11.3 million
0.18µm process
75mm² die
Cyrix III 700 MMX 3DNow!
(Samuel/C5)
2001?		370 pins
700MHz (100x7.0)
1.9v or 2.0v		Socket 37064KB data (4-way)
64KB instruction (2-way)		11.3 million
0.18µm process
75mm² die
C3 733A MMX 3DNow!
(Samuel 2/C5B)
March 25, 2001 - {$54}		370 pins
733MHz (133x5.5)
1.5v or 1.6v		Socket 37064KB data (4-way)
64KB instruction (2-way)
64KB on-Die L2 (4-way exclusive)
* ?GB cacheable		15.2 million
0.15µm process
52mm² die
C3 750A MMX 3DNow!
(Samuel 2/C5B)
March 25, 2001		370 pins
750MHz (100x7.5)
1.5v or 1.6v		Socket 37064KB data (4-way)
64KB instruction (2-way)
64KB on-Die L2 (4-way exclusive)
* ?GB cacheable		15.2 million
0.15µm process
52mm² die
C3 800A MMX 3DNow!
(Samuel 2/C5B)
2001		370 pins
800MHz (100x8.0)
1.6v		Socket 37064KB data (4-way)
64KB instruction (2-way)
64KB on-Die L2 (4-way exclusive)
* ?GB cacheable		15.2 million
0.15µm process
52mm² die
C3 850A MMX 3DNow!
(Samuel 2/C5B)
[not released]		370 pins
850MHz (100x8.5)
1.6v		Socket 37064KB data (4-way)
64KB instruction (2-way)
64KB on-Die L2 (4-way exclusive)
* ?GB cacheable		15.2 million
0.15µm process
52mm² die
C3 866A MMX 3DNow!
(Samuel 2/C5B)
[not released]		370 pins
866MHz (133x6.5)
1.6v		Socket 37064KB data (4-way)
64KB instruction (2-way)
64KB on-Die L2 (4-way exclusive)
* ?GB cacheable		15.2 million
0.15µm process
52mm² die
C3 800A MMX 3DNow!
(Ezra/C5C)
2001		370 pins
800MHz (100x8.0)
800MHz (133x6.0)
1.35v		Socket 37064KB data (4-way)
64KB instruction (2-way)
64KB on-Die L2 (4-way exclusive)
* ?GB cacheable		15.4 million
0.13/0.15µm process
52mm² die
C3 850A MMX 3DNow!
(Ezra/C5C)
2001		370 pins
850MHz (100x8.5)
1.35v		Socket 37064KB data (4-way)
64KB instruction (2-way)
64KB on-Die L2 (4-way exclusive)
* ?GB cacheable		15.4 million
0.13/0.15µm process
52mm² die
C3 866A MMX 3DNow!
(Ezra/C5C)
September 11, 2001		370 pins
866MHz (133x6.5)
1.35v		Socket 37064KB data (4-way)
64KB instruction (2-way)
64KB on-Die L2 (4-way exclusive)
* ?GB cacheable		15.4 million
0.13/0.15µm process
52mm² die
C3 900A MMX 3DNow!
(Ezra/C5C)
[not released]		370 pins
900MHz (100x9.0)
1.35v		Socket 37064KB data (4-way)
64KB instruction (2-way)
64KB on-Die L2 (4-way exclusive)
* ?GB cacheable		15.4 million
0.13/0.15µm process
52mm² die
C3 933A MMX 3DNow!
(Ezra/C5C)
[not released]		370 pins
933MHz (133x7.0)
1.35v		Socket 37064KB data (4-way)
64KB instruction (2-way)
64KB on-Die L2 (4-way exclusive)
* ?GB cacheable		15.4 million
0.13/0.15µm process
52mm² die
C3 1.0G MMX 3DNow!
(Ezra/C5C)
[not released]		370 pins
1000MHz (133x7.5)
1.35v		Socket 37064KB data (4-way)
64KB instruction (2-way)
64KB on-Die L2 (4-way exclusive)
* ?GB cacheable		15.4 million
0.13/0.15µm process
52mm² die