[ Main Menu / 486 Processor Pinout ]
169 pins - 17x17 Pin Grid Array - Zero Insertion Force socket or Low Insertion Force socket.
Bottom view of the processor (pin side). Pin One is in the lower left corner.
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S | o o o o o o o o o o o o o o o o o |
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R | o o o o o o o o o o o o o o o o o |
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Q | o o o o o o o o o o o o o o o o o |
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P | o o o / \ o o o |
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N | o o o | | o o o |
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M | o o o | | o o o |
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L | o o o | | o o o |
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K | o o o | | o o o |
| | BOTTOM VIEW | |
J | o o o | (pin side) | o o o |
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H | o o o | | o o o |
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G | o o o | | o o o |
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F | o o o | | o o o |
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E | o o o | | o o o |
| \ / |
D | o o o o\ / o o o |
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C | o o o o o o o o o o o o o o o o o |
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B | o o o o o o o o o o o o o o o o o |
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A \ o o o o o o o o o o o o o o o o o |
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The actual processor pinouts are contained in a PKZIP-compressed file called 486PIN.ZIP. The file contains an MSWorks 3.0 spreadsheet file (486PIN.WKS) and a plain text version (486PIN.TXT) that list the pin designations of the various 486 chips.
The chips included are:
This list is not comprehensive. Many chips are not listed here including AMD, IBM, Texas Instruments, and especially Cyrix. The Cyrix, IBM, and TI chips often share very similar pinouts though that doesn't mean that all three manufacturers produced all of each other's chips.
Only 486 processors are listed here. The Cyrix, IBM, and Texas Instruments 486DLC chips are 386/486 hybrids with a 386 pinout, and are not listed. The Intel Pentium OverDrive for 486 (P24T) is not listed because of its extra row of pins. For the P24T pinout, see Intel's Pentium OverDrive datasheet.
You'll need a PKZIP decompression program to extract the file. Winzip and Stuffit will work. As will PKZip 2.04g for DOS and PKZip 2.5 for OS/2.
The MSWorks 3.0 format should be readable to most all word processing programs. If not, there is a plain text version (486PIN.TXT) included.
The chart is also available online in HTML format: 486PIN2.HTM. Be aware that it is a large chart and may take a few seconds to load.
Even though I tried to be diligent, there are bound to be errors in this document. If you find any, please let me know: chare@rcn.com.
| A2 - A31 | Address pins. |
| A20M# | Address bit 20 Mask pin. |
| ADS# | Address Status. |
| AHOLD | Address Hold. |
| BE0 - BE3# | Byte Enable pins. |
| BLAST# | Burst Last. |
| BOFF# | Back Off input. |
| BRDY# | Burst Ready. |
| BRDYC# | Cache Burst Ready. |
| BREQ | Bus Request. |
| BS8# | Bus Size 8. |
| BS16# | Bus Size 16. |
| CACHE# | Cache. |
| CLK | Clock input. Provides fundamental timing for the processor. |
| CLKMUL | Clock Multiplier pin (Bus Frequency). Usually 2.0x or 3.0x, though it can be 2.5x or 4.0x, depending on the chip. |
| D0 - D31 | Data pins. |
| D/C# | Data/Code. Primary bus cycle definition pin. |
| DP0 - DP3 | Data Parity pins. |
| EADS# | External Address Strobe. |
| FERR# | Floating Point Error. |
| FLUSH# | Cache Flush. |
| HITM# | Hit to a Modified line. |
| HLDA | Hold Acknowledge. |
| HOLD | Bus Hold request. |
| IGNNE# | Ignore Numeric Error. |
| INTR | Maskable Interrupt. |
| INV | Invalidate. |
| INVAL | Invalidate. |
| KEN# | Cache Enable. |
| KEY | Key pin. Non-functional pin to prevent incorrect CPU insertion. |
| LOCK# | Bus Lock. |
| M/IO# | Memory/Input-Output. Primary bus cycle definition pin. |
| MP# | Math-coprocessor Present. When pulled low, the processor enters a powered-down tristate mode, allowing the math-coprocessor to take control. |
| NMI | Non-Maskable Interrupt. |
| PCD | Page Cache Disable. |
| PCHK# | Parity Status. |
| PLOCK# | Pseudo-Lock. |
| PWT | Page Write-Through. |
| RDY# | Non-burst Ready. |
| RESET | Reset. |
| RPLSET0 | ?. |
| RPLSET1 | ?. |
| RPLVAL# | ?. |
| SMADS# | System Management Interrupt Address Strobe. |
| SMI# | System Management Interrupt. Allows processor to enter system management mode. |
| SMIACT# | System Management Interrupt Active. Indicates that processor is in system management mode. |
| SRESET | Soft Reset. |
| STPCLK# | Stop Clock. |
| SUSP# | Suspend. Same as STPCLK#. |
| SUSPA# | ?. |
| TCK | Test Clock. |
| TDI | Test Data Input. |
| TDO | Test Data Output. |
| TEST | Test pin. |
| TMS | Test Mode Select. |
| UP# | Upgrade Present. When pulled low, the processor enters a powered-down tristate mode, allowing an upgrade processor to take control. |
| VOLDET | Voltage Detect. |
| WB/WT# | Write-Back / Write-Through. |
| WM_RST | Warm Reset. |
| W/R | Write / Read. |