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APS-X84 Specific Tech Notes
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APS-X84 X-File VHDL examples

Foundation FTP Files
XILINX Foundation Tech Notes
Selected Xilinx App Notes
Foundation Info general Docs
Selected Foundation Schematic Capture Docs
Foundation XVHDL Docs
Foundation Simulator Docs
Selected ABEL Docs
XCELL Issues
Selected Xilinx Utilities
Selected XILINX FTP Files
Selected XILINX VHDL Examples

Selected ALDEC Tech Notes

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APS-X84 Tech Notes:

X84-AN-FS001 Metamor BUFG assignments and the X84 VHDL Divider Example

Selected XILINX Foundation Tech Notes:

Xilinx Solutions Database : Foundation: Additional/Supplemental documentation is available on the FTP and BBS sites.
     http://www.xilinx.com/techdocs/1611.htm

Xilinx Foundation Interface - Glossary of Terms
      http://www.xilinx.com/support/techsup/journals/foundatn/glossary.htm

Xilinx Foudation Software Series (4/1/96)
http://www.xilinx.com/prs_rls/foundatn.pdf

Xilinx Foundation Series Brochure (4/1/96)
    http://www.xilinx.com/products/software/found_sh.pdf

Running Foundation on a Network (6/96)
    http://www.xilinx.com/xcell/xl21/xl21-29.pdf

Foundation: What is the Service Pack and where can I get it?
http://www.xilinx.com/techdocs/1090.htm

Foundation Software Makes VHDL Easy (6/96)
http://www.xilinx.com/xcell/xl21/xl21-22.pdf

Xilinx Foundation Interface - Getting Started
http://www.xilinx.com/support/techsup/journals/foundatn/start.htm

Xilinx Solutions Database : Foundation XVHDL: Using RAM and ROM in XC4000 devices
http://www.xilinx.com/techdocs/1485.htm

University Program Price List
http://www.xilinx.com/xup/ubroch/univpric.pdf

Xilinx Solutions Database : Foundation Install: Where can I find XABEL program to install it?
http://www.xilinx.com/techdocs/1797.htm

Xilinx Solutions Database : Foundation VHDL: Can I use a testbench for VHDL-file simulation?
http://www.xilinx.com/techdocs/1612.htm

Xilinx Solutions Database : Foundation XVHDL: Using XBLOX
     http://www.xilinx.com/techdocs/1484.htm

Xilinx Solutions Database : Foundation: Importing Orcad Symbols to Foundation
    http://www.xilinx.com/techdocs/1601.htm

Xilinx Solutions Database : XABEL/FOUNDATION: What is needed to compile a design containing XABEL blocks
    http://www.xilinx.com/techdocs/1388.htm

Xilinx Solutions Database : PPR/Foundation: Duplicate name errors when guiding designs entered in Foundation
    http://www.xilinx.com/techdocs/1382.htm

Xilinx Solutions Database : Foundation XVHDL: Using Global Buffers
    http://www.xilinx.com/techdocs/1375.htm

Xilinx Solutions Database : Foundation XVHDL: Using pullups and pulldowns
     http://www.xilinx.com/techdocs/1366.htm

Xilinx Solutions Database : Foundation: BTRIEVE 1002 or memory allocation error on XC4000E project
     http://www.xilinx.com/techdocs/1236.htm

Xilinx Solutions Database : Foundation Schematic: How to quickly locate nets in a schematic
     http://www.xilinx.com/techdocs/1545.htm

Xilinx Solutions Database : Foundation Install: shadow caused segment load failure lm_acs.dll
     http://www.xilinx.com/techdocs/1542.htm

Xilinx Solutions Database : Foundation XVHDL: Using Timespecs
    http://www.xilinx.com/techdocs/1487.htm

Xilinx Solutions Database : Foundation: Importing Viewlogic designs with multi-page macros
     http://www.xilinx.com/techdocs/1463.htm

Xilinx Solutions Database : Foundation XVHDL: Using Global Set/Reset and STARTUP
     http://www.xilinx.com/techdocs/1376.htm

Xilinx Solutions Database : Foundation XVHDL: How to use I/O Flip-Flops
     http://www.xilinx.com/techdocs/1373.htm

Xilinx Solutions Database : Foundation: Keylock must be upgraded after an upgrade from Win3.1 to Win95
         http://www.xilinx.com/techdocs/1291.htm

Xilinx Solutions Database : Foundation: How to move a project around
     http://www.xilinx.com/techdocs/1056.htm

Xilinx Solutions Database : WIN32S problems after installing Foundation (win32s v1.30a) - OE20.EXE, unexpected DOS
http://www.xilinx.com/techdocs/946.htm

Xilinx Solutions Database : Foundation XVHDL: Error #036 - Design too large
     http://www.xilinx.com/techdocs/2021.htm

Xilinx Solutions Database : Foundation XVHDL: How to use Wide-Edge Decoders
     http://www.xilinx.com/techdocs/1839.htm

Xilinx Solutions Database : Foundation: Adding parts and speed grades to the selection menus
     http://www.xilinx.com/techdocs/1507.htm

Xilinx Solutions Database : Foundation XVHDL: Using Latches
     http://www.xilinx.com/techdocs/1486.htm

Xilinx Solutions Database : Foundation XVHDL: How to specify FAST Slew rate
     http://www.xilinx.com/techdocs/1377.htm

Xilinx Solutions Database : Foundation XVHDL: How to use Bidirectional I/O
     http://www.xilinx.com/techdocs/1374.htm

Xilinx Solutions Database : Foundation XVHDL: How to lock down I/O pins
    http://www.xilinx.com/techdocs/1372.htm

Xilinx Solutions Database : Foundation: VHDL entry option is not selectable
    http://www.xilinx.com/techdocs/984.htm

Xilinx Solutions Database : Foundation: is there Windows 95, Windows NT, OS/2 support?
    http://www.xilinx.com/techdocs/910.htm

Xilinx Solutions Database : Design Manager: System Error, Unhandled Exception: ERROR_FILE_NOT_FOUND
     http://www.xilinx.com/techdocs/752.htm

Xilinx Solutions Database : Foundation XABEL: "XABEL is not installed" error when synthesizing ABELcode
     http://www.xilinx.com/techdocs/1978.htm

Xilinx Solutions Database : Foundation XVHDL: Setting NODELAY property on inputs
     http://www.xilinx.com/techdocs/1840.htm

Xilinx Solutions Database : Foundation Simulator: Where are custom Formulas stored?
     http://www.xilinx.com/techdocs/1798.htm


Xilinx Solutions Database : Foundation XVHDL: missing TNM attribute will cause XNFPREP Error 7845
     -http://www.xilinx.com/techdocs/1689.htm

Xilinx Solutions Database : Foundation: Connecting a symbol bus pin to a bus of different width
     http://www.xilinx.com/techdocs/1501.htm

Xilinx Solutions Database : Where can you get a listing of Synopsys XSI Library Components
     http://www.xilinx.com/techdocs/1204.htm

Xilinx Solutions Database : Foundation: Importing a Viewlogic design with a user library
     http://www.xilinx.com/techdocs/1068.htm

Xilinx Foundation Interface - Top Solutions
     http://www.xilinx.com/support/techsup/journals/foundatn/topsol.htm

File Download: Files/Patches/Information on the Foundation-Series Software 89KB FPGA/EPLD Device ...
    http://www.xilinx.com/support/techsup/ftp/htm_index/sw_foundation.htm

Xilinx Product Spotlight : Foundation Series Software, Easy VHDL Synthesis
     http://www.xilinx.com/spot/fnd.htm

Press Release : Xilinx & NeoCAD Merge
http://www.xilinx.com/prs_rls/neocad.pdf

Xilinx Development Systems Packages (v1.0, 6/1/96)
http://www.xilinx.com/partinfo/dev_sys2.pdf

Xilinx Solutions Database : Foundation Simulator: How to assign a value to a bus using Formulas
     http://www.xilinx.com/techdocs/1623.htm

Xilinx Solutions Database : Foundation Install: Hangs when displaying "Attaching Libraries"
     http://www.xilinx.com/techdocs/1525.htm

Xilinx Solutions Database : Foundation: Can't print schematics to network printer under Windows 95
     http://www.xilinx.com/techdocs/1355.htm

Xilinx Solutions Database : Foundation Timing simulation : BAX file design> does not exist XACT6 Design Manager process ?
    http://www.xilinx.com/techdocs/1184.htm

Xilinx Solutions Database : Foundation: Possible cause of XNFMERGE Warning 285
     http://www.xilinx.com/techdocs/1043.htm

Xilinx Foundation Interface - Tips and Techniques
     http://www.xilinx.com/support/techsup/journals/foundatn/tips.htm

Xilinx Solutions Database : Foundation: PPR error 5812 on imported Viewlogic design with CST file
     http://www.xilinx.com/techdocs/951.htm

Xilinx Solutions Database : XNFPREP error 3527: possible causes if using Foundation
     http://www.xilinx.com/techdocs/942.htm

Xilinx Solutions Database : Foundation Simulator: macro outputs always 'Z' during simulation
     http://www.xilinx.com/techdocs/939.htm

Xilinx Solutions Database : Foundation: Importing Viewlogic schematic could change some bus names
     http://www.xilinx.com/techdocs/936.htm

Xilinx Solutions Database : Foundation: Service Pack Install - Setup will not run
    http://www.xilinx.com/techdocs/1952.htm

Xilinx Solutions Database : Foundation: "File specified in $FILE parameter is missing" when pushing into macro
     http://www.xilinx.com/techdocs/1950.htm

Xilinx Solutions Database : Foundation Schematic: Adding Attributes - LOC, X, etc.
     http://www.xilinx.com/techdocs/1938.htm

Xilinx Solutions Database : Foundation: After unzipping archived project, errors updating xnf netlist
http://www.xilinx.com/techdocs/1835.htm

Xilinx Solutions Database : Design Manager 6.0.1: PPR - "Error XLM:KEY_NOT_FOUND" (LPT Conflict). Using Win 95.
     http://www.xilinx.com/techdocs/1664.htm

Xilinx Solutions Database : Foundation: How to generate a schematic from an XNF file
    http://www.xilinx.com/techdocs/1586.htm

Xilinx Solutions Database : Foundation: Changing title block information on schematics
     http://www.xilinx.com/techdocs/1518.htm

Xilinx Solutions Database : Foundation Install Error: VXD driver Daikon.386 missing
     http://www.xilinx.com/techdocs/1512.htm

Xilinx Solutions Database : Foundation: BTRIEVE error 11: specified file name is invalid.
     http://www.xilinx.com/techdocs/1502.htm

Xilinx Solutions Database : Foundation XVHDL: How to control the # of BUFGs which are automaticallyinserted.
    http://www.xilinx.com/techdocs/1473.htm

XACT FTP FILES

desmgr.pdf 1,460KB Design Manager Flow Engine Reference / User Guide
dsref1.pdf 907KB Development System Reference Guide Volume 1
dsref2.pdf 1,796KB Development System Reference Guide Volume 2
dsref3.pdf 1,498KB Development System Reference Guide Volume 3
dsuser.pdf 1,434KB Development System Users Guide
floorpln.pdf 1,787KB Floorplanner Reference/User Guide
hardware.pdf 1,221KB Hardware and Peripherals User Guide
hdlsynth.pdf 2,212KB HDL Synthesis For FPGAs Design Guide
hdwdebug.pdf 2,881KB Hardware Debugger Reference/User Guide
hw130doc.pdf 329 kB XACTstep HW-130 Programmer User Guide For All Platforms Uploaded: 02-13-97
install.pdf 662KB Getting Started Installation Guide (XACT 5.2.x/6.0.x)
library.pdf 4,406KB Libraries Guide (for 2000, 3000, 4000, and 7000)
libsupl.pdf 1,448KB Libraries Supplement Guide (for XC4000E and 5200)
promfile.pdf 649KB PROM File Formatter Reference/User Guide
timing.pdf 3,174KB Timing Analyzer Reference/User Guide
xblox.pdf 1,030KB X-BLOX Reference/User Guide
xnfspec.pdf 390KB Xilinx Netlist Format (XNF) Specification Version 6.1 June 1, 1995
xnfspecs_61.tar.Z 850KB Postscript files of the XNF Specification. This file is compressed and tar'ed.

FTP Foundation Files:

xfpga.zip 89KB FPGA/EPLD Device symbols library for Board Level Simulation
fdn7000.zip 702KB Xilinx XC7000 Library Patch that fixes problems found on several XC7000 library symbols
w32s13c.zip 3037KB Win32s version 1.30C This version fixes various Foundation issues
servpack.txt 11KB Contains information and installation instructions for the Service Pack.
whatsnew.hlp 229KB Help file containing information on Parts A and B of the Service Pack. This file is contained in SPXA.EXE and SPXB.EXE, so there is no need to download this if you have downloaded SPXA.EXE or SPXB.EXE.
whatnewx.hlp 13KB Help file containing information on Part V of the Service Pack. This file is contained in SPXV.EXE, so there is no need to download this if you have downloaded SPXV.EXE.
spxa.exe 4314KB Part "A" of the Service Pack. Contains updates to the Schematic Tool, Symbol Editor, Project Manager, and HDL Editor.
spxb.exe 1894KB Part "B". Contains a new version of the Simulator.
spxv.exe 3240KB Part "V". Contains a new version of the XVHDL Compiler (v2.4.4).
fnddoc1a.exe 857KB Version 1a of the Documentation Update Pack; supercedes version 1. This is an optional supplement to the Service Pack.
fnddoc1a.txt 3KB Contains information and suggested instal- lation location for the Documentation Update Pack.

Foundation General
fndtut.zip 1,733KB Windows 3.1.x/95 based tutorials on using the Xilinx Founadtion design entry software. (For all Xilinx families).
masttut.zip 1,239KB Windows 3.1.x/95 based tutorial interface. In order to use this software you will need to download modules from the /modules directory.
config.pdf 1,112KB Foundation Configuration Information
manpcm.pdf 734KB Foundation Design Process Management (How to use Project Manager for Foundation)
notes.pdf 413KB Misc. notes on using the Foundation tools
xlxman.pdf 444KB Foundation-Xilinx Interface Guide

Foundation XVHDL
manhde.pdf 798KB Foundation HDL Editor Users guide
vhdl_mug.pdf 838KB Metamore version 2.3 Users Guide (VHDL Compiler for Foundation toolset)
mentor.pdf 2,671KB Mentor Graphics Interface/Tutorial Guide

Foundation Schematic
aldectut.zip 495KB Tutorial for using the Foundation design entry software (Schematic and Symbol entry, Simulation, more) For all Xilinx families.
mansc.pdf 5,530KB Foundation Schematic Editor Users Guide

Foundation Simulator
mansim.pdf 3,655KB Foundation Logic Simulator Users Guide
timesim.pdf 154KB Foundation Timing Simulation Tutorial

Foundation XACT
xacttut.zip 4,712KB Windows 3.1.x/95 based tutorials on using the XACT-CPLD software for targeting the XC2000, XC3000, XC4000, XC5200 and XC7000 families.
cdmtutor.zip 340KB Tutorial for the XACT-CPLD Design Manager Interface. (XC9500 family)
ceztutor.zip 405KB Tutorial for the XACT-CPLD EZTAG 9500 downloading software.
cfetutor.zip 165KB Tutorial for the XACT-CPLD Flow Engine interface. (Xc9500 family)
ctatutor.zip 417KB Tutorial for the XACT-CPLD Timing Analyzer interface. (XC9500 family)
dmtutor.zip 336KB Tutorial for using the XACT-Step Design Manager interface. (XC2000, XC3000, XC4000, XC5200 and XC7000 families)
fetutor.zip 165KB Tutorial for using the XACT-Step Flow Engine interface. (XC2000, XC3000, XC4000, XC5200 and XC7000 families)
fptutor.zip 1,058KB Tutorial for using the XACT-Step Floorplanner interface. (XC3000, XC4000, XC5200 families)
hddg.zip 703KB Tutorial for High Density Design Methodologies using FPGAs.
hdtutor.zip 394KB Tutorial for using the XACT-Step Hardware Debugger to program Xilinx FPGAs.
pftutor.zip 379KB Tutorial for using the XACT-Step PROM File Formatter to create PROM files from FPGA bit streams.
tatutor.zip 417KB Tutorial for using the XACT-Step Timing Analyzer to find the timing performance of your Xilinx design. (XC3000, XC4000, XC5200 and XC7000 families)
promfile.pdf 649KB PROM File Formatter Reference/U

ABEL
tbook.zip 435KB Tutorial for using the XABEL-CPLD Software for the XC7000 and XC9500 families.
abeltut.zip 1,673KB Windows 3.1.x/95 based tutorials on using the XABEL-CPLD software. (for XC7000 and XC9000 families)
cpldtut.zip 2,585KB Windows 3.1.x/95 based tutorials on using the XACT-CPLD software for targeting the XC9500 family.
manhde.pdf 798KB Foundation HDL Editor Users guide
xabel.pdf 1,459KB Xilinx ABEL User Guide

XCELL ISSUES

xcell17.pdf 503 kB XCELL Journal #17 Q2/95 For All Platforms Uploaded: 03-07-97
xcell18.pdf 976 kB XCELL Journal #18 Q3/95 For All Platforms Uploaded: 03-07-97
xcell19.pdf 929 kB XCELL Journal #19 Q4/95 For All Platforms Uploaded: 03-07-97
xcell20.pdf 1516 kB XCELL Journal #20 Q1/96 For All Platforms Uploaded: 03-07-97
xcell21.pdf 1538 kB XCELL Journal #21 Q2/96 For All Platforms Uploaded: 03-07-97
xcell22.pdf 2179 kB XCELL Journal #22 Q3/96 For All Platforms Uploaded: 03-07-97
xcell23.pdf 1080 kB XCELL Journal #23 Q4/96 For All Platforms Uploaded: 03-07-97
xcell24.pdf 1029 kB XCELL Journal #24 Q1/97 See HTML

3rd party interfaces documetation that are supported by Xilinx. **Note: See /pub/documentation/misc/lit.txt for a full listing of available Xilinx literature availible upon request.

VHDL Examples (Not specific to Foundation but included anyway)

xsi_vhdl.tar.Z 5115KB VHDL Examples with SIM, SYN and MRA files in Work directory
xsi_vhdl_no_wk.tar.Z 3253KB VHDL Examples without SIM, SYN and MRA files in Work directory

UTILS

timp.zip 242KB XC7000 static timing analyzer (PC version)
am2xc.exe 43KB Self-extracting ZIP file to convert MACH to Xilinx
power.zip 95KB Power Consumption Estimation utility for 2k, 3k and 4k parts
lfsr.zip 37KB Utility to aid in designing linear feedback shift registers.
ioloc.zip 94KB Reads IO locations from LCA file and creates CST file for locking IOs. Also creates macro to backannotate IO locations to Viewlogic schematic.
xnfdif.zip 70KB Compares 2 XNF or MAP files
asic_est.zip 807KB Xilinx ASIC Estimator Utility DOS based tool which estimates the cost advanteges of FPGAs over traditional ASIC designs. For DOS 5.0 and better.
dn_ld.zip 66KB C source code for serial download of .bit file
hex2bits.zip 13KB Converts Stripped PROM file ( output of STRIPHEX ) to rawbits ( ascii '1's and '0's) format. PC Version.
makesrc.zip 43KB Generates C or Assembly code from an MCS format PROM file for embedded applications PC version.
mkbs.zip 8KB Generates a hex file for 'broadside' loading of LCAs in the slave configuration mode.
pconfig.zip 18KB Generates a PROM file from a data file containing byte ( hex ) or bit (rawbits) data
psplit.zip 23KB Breaks up large PROM file in to a number of smaller PROM files. PC Version.
stag.zip 8KB Converts Motorola extended 'S' record file to JEDEC.
striphex.zip 15KB Strips PROM programmer related information from a PROM file (PC version).

APP NOTES (can import Vielogic and Orcad files into FOUNDATION)

xapp007o.zip 27KB Boundary Scan Emulator for XC3000 v2.03, Implemented in OrCAD 386+ V1.10 Unified Libraries
xapp007v.zip 33KB Boundary Scan Emulator for XC3000 v2.03, Implemented in Viewdraw-LCA Unified Libraries
xapp014o.zip 70KB Ultra-Fast Synchronous Counters v1.02, Implemented in OrCAD 386+ V1.10 Unified Libraries
xapp014v.zip 61KB Ultra-Fast Synchronous Counters V.1.01, Implemented in Viewdraw-LCA Unified Libraries
xapp044o.zip 39KB High-Performance RAM based FIFO V.1.00, Implemented in Orcad 386+ V1.10
xapp002v.zip 197KB Loadable Up/Down Counters, 8 to 24 bits long V.2.0.1, Implemented in Viewdraw-LCA Unified Libraries
xapp050o.zip 417KB Crossbar Switch in XC4000 V.1.00, Implemented in Orcad 386+ V1.10
xapp050v.zip 362KB Crossbar Switch in XC4000 V.1.00, Implemented in Viewdraw-LCA Unified Libraries
xapp001o.zip 100KB 60 MHz Counters, 8 to 24 bits long V.2.0.1, Implemented in OrCAD 386+ V1.10 Unified Libraries
xapp005o.zip 68KB Register-Based FIFO for XC3000 V.2.0.1, Implemented in OrCAD 386+ V1.10 Unified Libraries
xapp005v.zip 87KB Register-Based FIFO for XC3000 V.2.0.1, Implemented in Viewdraw-LCA Unified Libraries
xapp009o.zip 26KB Frequency Synthesizer, FSK Modulator V.2.0.1, Implemented in OrCAD 386+ V1.10 Unified Libraries
xapp021v.zip 107KB 150 MHz Dual-Prescaler Presettable Counters for XC3000. V.2.01, Implemented in Viewdraw-LCA Unified Libraries
xapp023o.zip 64KB Accelerating Loadable Counters in XC4000 V.1.01, Implemented in OrCAD 386+ V1.10 Unified Libraries
xapp004o.zip 225KB Loadable Binary Counters, 16, 32 bits long V.2.0.1, Implemented in OrCAD 386+ V1.10 Unified Libraries
xapp009v.zip 31KB Frequency Synthesizer, FSK Modulator V.2.0.1, Implemented in Viewdraw-LCA Unified Libraries
xapp021o.zip 90KB 150 MHz Dual-Prescaler Presettable Counters for XC3000. V.2.01, Implemented in OrCAD 386+ V1.10. Unified Libraries
xapp022o.zip 12KB Adders, Subtractors, and Accumulators in XC3000. V.1.01, Implemented in OrCAD 386+ V1.10. Unified Libraries
xapp022v.zip 17KB Adders, Subtractors, and Accumulators in XC3000. V.1.01, Implemented in Viewdraw-LCA Unified Libraries
xapp023v.zip 78KB Accelerating Loadable Counters in XC4000 V.1.01, Implemented in Viewdraw-LCA Unified Libraries
xapp026o.zip 23KB Multiplexers and Barrel Shifters in XC3000. V.1.01, Implemented in OrCAD 386+ V1.10 Unified Libraries
xapp026v.zip 32KB Multiplexers and Barrel Shifters in XC3000. V.1.01, Implemented in Viewdraw-LCA Unified Libraries
xapp028o.zip 5KB Frequency/Phase Comparator for Phase-Locked Loops. V.1.01, Implemented in OrCAD 386+ V1. Unified Libraries
xapp028v.zip 6KB Frequency/Phase Comparator for Phase-Locked Loops. V.1.01, Implemented in Viewdraw-LCA Unified Libraries
xapp029o.zip 6KB Serial Code Conversion Between BCD and Binary V.1.01, Implemented in OrCAD 386+ V1.10 Unified Libraries
xapp029v.zip 8KB Serial Code Conversion Between BCD and Binary V.1.01, Implemented in Viewdraw-LCA Unified Libraries
xapp048o.zip 39KB Xilinx Guided Tour for XACT 5.0 V.1.00, Implemented in OrCAD 386+ V1.10 Unified Libraries
xapp048v.zip 37KB Xilinx Guided Tour for XACT 5.0 V.1.00, Implemented in Viewdraw-LCA Unified Libraries
xapp002o.zip 187KB Loadable Up/Down Counters, 8 to 24 bits long V.2.0.1, Implemented in OrCAD 386+ V1.10 Unified Libraries
xapp003v.zip 375KB Synchronous Presettable Up and Down Counters, 8, 12, and 16 bits long V.2.0.1, Implemented in Viewdraw-LCA Unified Libraries
xapp004v.zip 282KB Loadable Binary Counters, 16, 32 bits long V.2.0.1, Implemented in Viewdraw-LCA Unified Libraries
xapp036a.zip 6KB DRAM Controller for XC7200 ABEL and .pld Behavioral design files for a 4-port memory controller. Fits in an XC7236.
xapp049a.zip 18KB Pentium/Synchronous DRAM Controller Behavioral Design Example for EPLDs ABEL files, V.1.00
xap4007v.zip 29KB Boundary Scan Emulator for XC3000 Implemented in Viewdraw-LCA Pre-Unified Libraries
xap4021v.zip 114KB 150 MHz Dual-Prescaler Presettable Counters for XC3000. V.1.00, Implemented in Viewdraw-LCA Pre-Unified Libraries
xap4006v.zip 84KB RAM-Based FIFO for XC4000 V.1.10, Implemented in Viewdraw-LCA Pre-Unified Libraries
xap4009v.zip 40KB Frequency Synthesizer, FSK Modulator V.1.10, Implemented in Viewdraw-LCA Pre-Unified Libraries
xapp006v.zip 84KB RAM-Based FIFO for XC4000 V.1.10, Implemented in Viewdraw-LCA Unified Libraries
xap4005v.zip 101KB Register-Based FIFO for XC3000 V.1.10, Implemented in Viewdraw-LCA Pre-Unified Libraries
xap4004v.zip 350KB Loadable Binary Counters, 16, 32 bits long V.1.10, Implemented in Viewdraw-LCA Pre-Unified Libraries
xap4003v.zip 196KB Synchronous Presettable Up and Down Counters, 8, 12, and 16 bits long V.1.10, Implemented in Viewdraw-LCA Pre-Unified Libraries
xap4002v.zip 273KB Loadable Up/Down Counters, 8 to 24 bits long V.1.10, Implemented in Viewdraw-LCA Pre-Unified Libraries
xap4001v.zip 149KB 60 MHz Counters, 8 to 24 bits long V.1.10, Implemented in Viewdraw-LCA Pre-Unified Libraries

DSP APPS

fft.zip 12 kB This is an example VHDL design of a Fast Fourier Transform for a Digital Processing System. Please refer to the enclosed readme.txt file for further details.
xamfir.zip 832 kB Word .DOC files for FIR filter application
dspdev.ppt 1083 kB Xilinx Applications DSP Presentation
fir_filt.zip 308 kB Viewlogic files for "16-tap, 8-bit FIR Filter" application note For All Platforms Uploaded: 12-02-96
xdsp.tar.Z 7653 kB DSP Toolbox library. Created for use with Mentor A.4 or B.x For All Unix Uploaded: 03-10-97

FPGA Applications involving FIFO (First-In First-Out) Memory

4kefifo.exe 169KB Design files for XC4000E FIFOs App. Note
advfdemo.zip 59KB LCA, BIT, MCS, RPT Files for ADVFIFO
advfifo.zip 100KB Advanced Megabit x N FIFO Xilinx DataBook, "Megabit FIFO in 2 Chips..."
mbitfifo.zip 99KB Megabit x N FIFO Xilinx DataBook, "Megabit FIFO in 2 Chips..."
mbitjet.exe 993KB Self-extracting archive. Contains HP Laser Jet files to print out schematics for the Megabit FIFO.

Miscellaneous Programmable Logic Applications

rs-232.zip 213KB Design files to accompany the application note: RS-232 Based Communications with Xilinx FPGAs. Contains Viewlogic schematics in Pre-Unified Libraries, post-script files.
pc_isa.zip 50KB files to accompany "Configuring FPGAs over a Processor Bus" application note
bcdcnt.zip 59KB ViewLogic Schematics for "Ten Digit Synchronous BCD Counter", targeted for 3142a
psmfiles.exe 44KB Viewlogic schematic files for "Dynamic Micro- controller in an XC4000 FPGA" App note.
counter.pld 1KB Counter file mentioned on p.1-4 of XEPLD Design Guide, April 1994
hd16bitb.zip 9KB High speed 16-bit counter (9 CLBs)
hd16bit.zip 17KB High-density 16-bit counter and accumulator hard macros (8 CLBs each)
pwm.zip 8KB Viewlogic design files for "Pulse Width Modulation in Xilinx Programmable Logic" application note For All Platforms Uploaded on Mon Dec 2 13:41:22 PST 1996

Applications Involving PCI

rev1e.zip 503KB Viewlogic version and Verilog source code for XC3164 designs in app note, "Designing Flexible PCI Interfaces with Xilinx EPLDs."
pci_abel.zip 3KB ABEL source code for XC73108 and XC7354 designs in application note "Designing Flexible PCI Interfaces w/ Xilinx EPLD's"
pci_v.zip 16KB Verilog/HDL source code for XC3164 designs in application not "Fully Compliant PCI Interface in XC3164A-2"
pci_vhdl.zip 3KB VHDL source code for XC73144 Target Interface design in application note "Designing Flexible PCI Interfaces w/ Xilinx EPLD's"
7300ckl.zip 8KB XC7300-10 PCI Component Electrical Checklist (Word 6.0)
3100ackl.zip 3KB XC3100A-2 PCI Component Electrical Checklist (Word 6.0)
pciapp.zip 25KB Notes on PCI applications

pcmcia.zip 160KB Sample PCMCIA modem card design. Not simulated or implememted

FPGA Applications Involving Arithmetic Functions

divide4k.zip 83KB 16 x 16 Divide function in 4000 series LCA Implemented with FutureNet/Silos
add16.zip 43KB 16-Bit Conditional Sum Adder Xilinx Data Book, "Conditional Sum Adder ..."
a16bit.zip 50KB 16-Bit Adder with Carry Lookahead Xilinx Data Book, "Adders and Comparators" Implemented in Dash-LCA
a16jet.exe 404KB Self-extracting archive. Contains HP Laser Jet files to print out schematics for the Adder with Carry Lookahead.

Plug and Play Application Files

mnp_upd.exe 25KB Updated schematics for version 0.90 of pnp_v90.exe, Plug and Play design.
pnp_v090.exe 239KB Plug and Play ISA interface using the Xilinx XC4003/5 FPGA. Application Note Version: 0.90. Design Last Updated: 19-MAY-95
pnpabel.zip 6KB Plug and Play ABEL files

ALDEC Foundation Tech Notes:

Installation Questions
General Question
Schematic
Simulation
Synthesis
Installing ACTIVE-CAD 2.2 & XILINX Foundation on the Same PC
Manual Installation of Foundation software
Importing Orcad Schematics into ACTIVE-CAD
Multiple FPGA Designs
Hierarchical ABEL6 Top Level Projects
Creating multi-file VHDL macros in ACTIVE-CAD
Win32s Application Note
Changing Xilinx Family
Creating Macros from a Netlist
Full List of Hot Keys
Analyzing Timing Violations in Xilinx Designs
Recovering the Contents of Damaged Libraries
On-line Documentation and Help Files
Add-on Libraries and Library Updates
All Updates and Service Packs
Free Demos and Utilities

GO TO ALDEC

APS Utilities:

Coming Soon: Metamor Compiler Add-on and extended help system

Coming Soon: X84 Windows control file (willrun with X84 examples):