CONTENTS This issue's website picks:  Very useful and inclusive link to various EDA vendors and subjects. Steve (PLJ's caretaker) is also a regular poster to the comp.arch.fpga newsgroup. EDN Magazine A nice central location for looking up all the new products and articles which EDN produces. APS News Letter Introduced By: Richard Schwarz This is APS's first publication of The APS EDA Newsletter which will be a quarterly newsletter discussing various topics having to do with the FPGA /PLD/ASIC industry. It is hoped that the newsletter will be a guide for many new programmers and engineers. The newsletter will discuss any new APS releases, tech notes and examples, as well as containing a VHDL discussion topic section and a website section pointing out various websites which we have found to be useful. We encourage comments and suggestions from our readers. We will also publish selected examples, comments, or articles submitted by our readers. To submit such material go the Feedback section. We hope to keep our information short and to the point. Announcements of the issues will be sent out via e-mail to APS customers and to anyone else interested. To subscribe simply send us an EMAIL with EDA NEWSLETTER-SUBSCRIBE in the subject header. The email will be a simple announcement with an accompanying URL listing. We will not pass on any EMAIL address lists to any other agents. APS-X84 FPGA KIT NEWS The APS Foundation kits have been a great success. It was the goal of APS to provide a viable FPGA toolset for new programmers which contained all of the following elements: 1) HDL synthesis 2) Schematic Capture Synthesis 3) Routing Capabilities 4) Post Routing Simulation 5) Real Time practical Implementation Platform 6) Reasonable Cost All of these goals have been met, and more with the APS-X84 FPGA kits. THe Foundation VHDL compiler and Aldec Schematic capture are coupled with XILINX's XACT router to provide an excellent shrink wrapped package of tools. Once the FPGA is synthesized and routed, the APS-X84 development board which has an ISA bus connector, C code drivers, board schematics, and example files, the kit user is given access to a really useful implementation board which can be controlled real time in the PC using C control programs which the user can develop on systems probably already available to them. The X84 has a DISK DRIVE type power supply connector for stand alone mode and can be used with the XCHECKER cables which come in each kit. The FPGA is downloaded via the PC bus (in PC mode) or the XCHECKER in stand-alone mode using the bit files from the XACT router software. No translation is needed. In addition, XILINX has provided a VHDL tutorial in all the Foundation kits which come with VHDL. More information on these kits can be obtained at the following URL: http://www.erols.com/aaps/x84.html APS-X84 FPGA Tech Note Published A tech note describing the METAMOR VHDL compiler's use of global buffers was published in PFD format. This technote was published when it was found that the X84 Divider example (which comes with the X84 board) was recompiled, that the PIN assignments for the on board X84 timer line, which was used as a clock, was automatically being assigned as a Global Buffer by the METAMOR compiler. This is actually a nice feature of the Metamor compiler. It automatically assigns clock pins to the Global buffers, thus insuring that the design has the best possible clock distribution. The problem is however that, pin placement flexibility is lost. The automatic Global Buffer placement can be turned off, but not from the GUI. A file called METAMOR.ARG has to be created which will contain this and various other options. APS is in the process of writing a WINDOWS GUI utility which will automate these options also. It should be released in May 97 and will be available for download from our web page. |
  X84 Example
Files Release ScheduleThe APS-X84 X-Files example section has several examples which are being worked on by APS and are described below. Any engineer or VHDL programmer may submit examples with an explanation of the code and implementations. Examples will be available in zip and PDF formats. APS will put the examples into these formats for the authors. We especially encourage University and College students who have used the X84 in lab kits to post their labs and examples. The same Lab will only be listed once. Contact Richard Schwarz at aaps@erols.com to submit examples. Simple counter divider Example .....April 97 POD-ALYZER Logic Analyzer X84 Example......April 97 PN Sequence Generator Example....May 97 Using the X84 Stand Alone w the Xchecker Cable .....May 97 PN Filter Example ........June 97 The first two to be released will be the simple counter example, and the POD-ALYZER example which will both be the focus in our next newsletter. Interesting Threads The following newsgroups threads were of particular interest this quarter. If the subjects do not appear in the news group then do a search using DEJA-News for the subject. From: comp.arch.fpga Subject: Sole Source - An interesting discussion on the pricing strategy and problems encountered when the Silicon vendors are the only source of routing tools. From: comp.lang.vhdl Subject: OUT INOUT and BUFFER - A discussion of the use of these attributes in VHDL VHDL Discussion Topic: Using Aliases I was recently doing a VHDL project which required processing on long shift register chains of which I needed to manipulate several small chunks of the register runs. I could have continually accessed the parts using an explicit tag --say for instance RegChain(120 downto 118)-- but this method does not allow me an easy way to identify the chunk of register's purpose. It is also not very nice to look at or follow in the code. A very nice method is available in VHDL using ALIASES which allows programmers to assign symbols in VHDL which represent part or all of another SIGNAL.. This coding technique can make your code much more readable and save you a lot of speculation and reexamination time when writing your code. Here is how to declare an ALIAS: Lets say that the 120 downto 118 bits of the SIGNAL RegChain are a marker flag for a certain process. We could do the following: -- here is the long chain SIGNAL RegChain: STD_LOGIC_VECTOR(120 downto 0); -- followed by an alias. I like to place my aliases all together under the aliased signal ALIAS MarkerFlag: STD_LOGIC_VECTOR(2 downto 0) is RegChain(120 downto 118); Now you can reference the 120 downto 118 bits of RegChain by using the name MarkerFlag. I have found these ALIASes very useful. Perhaps you will also.Give them a try. FEEDBACK  APS Product News SPONSORS    And what paper would be complete without the comic section 
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